Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

172108306

1

T4

15

T1

6525

T5

14

full_word

19694391

1

T4

1100

T1

3251

T5

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	191802337	1			T4	1115		T1	9776		T5	22
auto[TlIntgErrCmd]	126	1			T71	11		T72	6		T112	11
auto[TlIntgErrData]	117	1			T71	8		T72	6		T112	9
auto[TlIntgErrBoth]	117	1			T71	11		T72	8		T112	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

179280766

1

T4

17

T1

8058

T5

1

auto[1]

12521931

1

T4

1098

T1

1718

T5

21

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	171785937	1			T4	9		T1	6523		T5	1
auto[TlIntgErrNone]	partial	auto[1]	322039	1			T4	6		T1	2		T5	13
auto[TlIntgErrNone]	full_word	auto[0]	7494664	1			T4	8		T1	1535		T2	2
auto[TlIntgErrNone]	full_word	auto[1]	12199697	1			T4	1092		T1	1716		T5	8
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T71	4		T72	1		T112	7
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T71	5		T72	4		T112	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T71	2		T199	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T72	1		T160	1		T200	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T71	1		T72	3		T112	4
auto[TlIntgErrData]	partial	auto[1]	55	1			T71	6		T72	3		T112	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T160	1		T198	1		T199	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T71	1		T112	1		T198	2
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T71	6		T72	4		T112	6
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T71	5		T72	3		T112	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T112	1		T198	1		T201	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T72	1		T196	1		T197	1