Unified Coverage Report :: Module :: spi_fwm_rxf_ctrl

Module : spi_fwm_rxf_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.06	100.00	94.87		100.00	97.37

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_rxf_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_fwmode.u_rxf_ctrl	98.06	100.00	94.87		100.00	97.37

---

Module Instance : tb.dut.u_fwmode.u_rxf_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.06	100.00	94.87		100.00	97.37

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.06	100.00	94.87		100.00	97.37

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	91.67	100.00					u_fwmode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_fwm_rxf_ctrl

	Line No.	Total	Covered	Percent
TOTAL		94	94	100.00
ALWAYS	80	3	3	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
ALWAYS	97	10	10	100.00
CONT_ASSIGN	116	1	1	100.00
ALWAYS	120	3	3	100.00
ALWAYS	131	7	7	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
ALWAYS	146	11	11	100.00
ALWAYS	160	4	4	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	181	41	41	100.00
ALWAYS	266	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_rxf_ctrl.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_rxf_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	2	2
81	1	1
84	1	1
87	1	1
90	1	1
91	1	1
93	1	1
97	1	1
98	1	1
99	1	1
100	1	1
102	1	1
103	1	1
104	1	1
106	1	1
107	1	1
110	1	1
			MISSING_ELSE
116	1	1
120	1	1
122	1	1
124	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	2	2
			MISSING_ELSE
			MISSING_ELSE
139	1	1
142	1	1
146	1	1
147	1	1
148	1	1
149	1	1
150	1	1
151	2	2
152	1	1
153	1	1
154	1	1
155	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
163	1	1
			MISSING_ELSE
167	1	1
171	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
190	1	1
194	1	1
195	1	1
196	1	1
197	1	1
199	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
217	1	1
218	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
232	1	1
233	1	1
234	1	1
236	1	1
243	1	1
244	1	1
246	1	1
247	1	1
248	1	1
255	1	1
256	1	1
266	1	1
267	1	1
268	1	1
270	1	1
271	1	1

---

Cond Coverage for Module : spi_fwm_rxf_ctrl

	Total	Covered	Percent
Conditions	39	37	94.87
Logical	39	37	94.87
Non-Logical	0	0
Event	0	0

 LINE       84
 EXPRESSION (spi_mode_i == FwMode)
            -----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       90
 EXPRESSION ((ptr_cmp[(PtrW - 1)] == 1'b1) && (ptr_cmp[(PtrW - 2):SDW] == '0))
             --------------1--------------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T2,T33
1	1	Covered	T1,T2,T11

 LINE       90
 SUB-EXPRESSION (ptr_cmp[(PtrW - 1)] == 1'b1)
                --------------1--------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T11

 LINE       90
 SUB-EXPRESSION (ptr_cmp[(PtrW - 2):SDW] == '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       100
 EXPRESSION (byte_enable == '0)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T104,T105
1	Covered	T1,T2,T3

 LINE       102
 EXPRESSION (wptr[(PtrW - 2):SDW] == sramf_limit)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T3,T33
1	Covered	T1,T2,T11

 LINE       116
 EXPRESSION (1'b1 == (&byte_enable))
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       120
 EXPRESSION (wptr[(PtrW - 1)] == rptr[(PtrW - 1)])
            -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T4,T1,T5

 LINE       135
 EXPRESSION (st == StWait)
            -------1------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       136
 EXPRESSION (cur_timer != '0)
            --------1--------

-1-	Status	Tests
0	Covered	T25,T104,T105
1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (cur_timer == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T25,T104,T105

 LINE       151
 EXPRESSION (pos == 2'((NumBytes - 1)))
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION ((byte_enable == '0) ? '1 : spi_device_pkg::sram_strb2mask(byte_enable))
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T1,T5

 LINE       167
 SUB-EXPRESSION (byte_enable == '0)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       194
 EXPRESSION (active && fifo_valid && ((!sramf_full)))
             ---1--    -----2----    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T2,T11,T33
1	1	1	Covered	T1,T2,T3

 LINE       207
 EXPRESSION (fifo_valid && ((!full_sramwidth)))
             -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T38,T39
1	1	Covered	T11,T23,T37

 LINE       230
 EXPRESSION (((!fifo_valid)) && timer_expired)
             -------1-------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T25,T104,T105

---

FSM Coverage for Module : spi_fwm_rxf_ctrl

Summary for FSM :: st

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	7	7	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StIdle	199	Covered	T4,T1,T5
StPop	195	Covered	T1,T2,T3
StUpdate	244	Covered	T1,T2,T3
StWait	217	Covered	T1,T2,T3
StWrite	212	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StIdle->StPop	195	Covered	T1,T2,T3
StPop->StWait	217	Covered	T1,T2,T3
StPop->StWrite	212	Covered	T1,T2,T3
StUpdate->StIdle	255	Covered	T1,T2,T3
StWait->StPop	227	Covered	T1,T2,T3
StWait->StWrite	232	Covered	T25,T104,T105
StWrite->StUpdate	244	Covered	T1,T2,T3

---

Branch Coverage for Module : spi_fwm_rxf_ctrl

	Line No.	Total	Covered	Percent
Branches		38	37	97.37
TERNARY	167	2	2	100.00
IF	80	2	2	100.00
IF	97	5	5	100.00
IF	120	2	2	100.00
IF	131	5	5	100.00
IF	146	5	5	100.00
IF	160	3	3	100.00
CASE	190	12	11	91.67
IF	266	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_rxf_ctrl.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_rxf_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	167	((byte_enable == '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	97	if ((!rst_ni))
-2-:	99	if (update_wptr)
-3-:	100	if ((byte_enable == '0))
-4-:	102	if ((wptr[(PtrW - 2):SDW] == sramf_limit))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T1,T5
0	1	1	1	Covered	T1,T2,T11
0	1	1	0	Covered	T1,T3,T33
0	1	0	-	Covered	T25,T104,T105
0	0	-	-	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	120	if ((wptr[(PtrW - 1)] == rptr[(PtrW - 1)]))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T1,T2,T11

	LineNo.	Expression
-1-:	131	if ((!rst_ni))
-2-:	133	if (timer_rst)
-3-:	135	if ((st == StWait))
-4-:	136	if ((cur_timer != '0))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T1,T5
0	1	-	-	Covered	T1,T2,T3
0	0	1	1	Covered	T1,T2,T3
0	0	1	0	Covered	T25,T104,T105
0	0	0	-	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	146	if ((!rst_ni))
-2-:	149	if (update_wdata)
-3-:	151	if ((pos == 2'((NumBytes - 1))))
-4-:	153	if (clr_byte_enable)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T1,T5
0	1	1	-	Covered	T1,T2,T3
0	1	0	-	Covered	T1,T2,T3
0	0	-	1	Covered	T1,T2,T3
0	0	-	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	160	if ((!rst_ni))
-2-:	162	if (update_wdata)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	190	case (st)
-2-:	194	if (((active && fifo_valid) && (!sramf_full)))
-3-:	207	if ((fifo_valid && (!full_sramwidth)))
-4-:	211	if (full_sramwidth)
-5-:	226	if (fifo_valid)
-6-:	230	if (((!fifo_valid) && timer_expired))
-7-:	243	if (sram_gnt)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle	1	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	-	-	-	-	-	Covered	T4,T1,T5
StPop	-	1	-	-	-	-	Covered	T11,T23,T37
StPop	-	0	1	-	-	-	Covered	T1,T2,T3
StPop	-	0	0	-	-	-	Covered	T1,T2,T3
StWait	-	-	-	1	-	-	Covered	T1,T2,T3
StWait	-	-	-	0	1	-	Covered	T25,T104,T105
StWait	-	-	-	0	0	-	Covered	T1,T2,T3
StWrite	-	-	-	-	-	1	Covered	T1,T2,T3
StWrite	-	-	-	-	-	0	Covered	T106,T44,T107
StUpdate	-	-	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	266	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T2