Unified Coverage Report :: Module :: prim_intr_hw

Module : prim_intr_hw

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_intr_rxf	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_rxlvl	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_txlvl	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_rxerr	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_rxoverflow	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_txunderflow	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_cmdfifo_not_empty	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_payload_not_empty	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_payload_overflow	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
tb.dut.u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_intr_rxf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_rxlvl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_txlvl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_rxerr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_rxoverflow

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_txunderflow

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_cmdfifo_not_empty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_payload_not_empty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_payload_overflow

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_readbuf_watermark

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_readbuf_flip

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_intr_tpm_cmdaddr_notempty

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_intr_rxf

SCORE	LINE
100.00	100.00

tb.dut.u_intr_rxlvl

SCORE	LINE
100.00	100.00

tb.dut.u_intr_txlvl

SCORE	LINE
100.00	100.00

tb.dut.u_intr_rxerr

SCORE	LINE
100.00	100.00

tb.dut.u_intr_rxoverflow

SCORE	LINE
100.00	100.00

tb.dut.u_intr_txunderflow

SCORE	LINE
100.00	100.00

tb.dut.u_intr_cmdfifo_not_empty

SCORE	LINE
100.00	100.00

tb.dut.u_intr_payload_not_empty

SCORE	LINE
100.00	100.00

tb.dut.u_intr_payload_overflow

SCORE	LINE
100.00	100.00

tb.dut.u_intr_readbuf_watermark

SCORE	LINE
100.00	100.00

tb.dut.u_intr_readbuf_flip

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
49	1	1
52	1	1
54	1	1
80	1	1
81	1	1
83	1	1

---

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_intr_tpm_cmdaddr_notempty

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
ALWAYS	60	4	4	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	2	2
61	2	2
			MISSING_ELSE
66	1	1
68	1	1
73	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_intr_rxf

SCORE	COND
100.00	100.00

tb.dut.u_intr_rxlvl

SCORE	COND
100.00	100.00

tb.dut.u_intr_txlvl

SCORE	COND
100.00	100.00

tb.dut.u_intr_rxerr

SCORE	COND
100.00	100.00

tb.dut.u_intr_rxoverflow

SCORE	COND
100.00	100.00

tb.dut.u_intr_txunderflow

SCORE	COND
100.00	100.00

tb.dut.u_intr_cmdfifo_not_empty

SCORE	COND
100.00	100.00

tb.dut.u_intr_payload_not_empty

SCORE	COND
100.00	100.00

tb.dut.u_intr_payload_overflow

SCORE	COND
100.00	100.00

tb.dut.u_intr_readbuf_watermark

SCORE	COND
100.00	100.00

tb.dut.u_intr_readbuf_flip

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T43,T122,T148

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T43,T122,T148
1	1	Covered	T43,T122,T148

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_intr_tpm_cmdaddr_notempty

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T43,T122,T148
1	0	Covered	T7,T13,T8

 LINE       68
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T43,T122,T148
1	0	Covered	T7,T13,T8

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T13,T23
1	1	Covered	T8,T43,T122

---

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_rxf

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_rxlvl

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_txlvl

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_rxerr

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_rxoverflow

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_txunderflow

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_cmdfifo_not_empty

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_payload_not_empty

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_payload_overflow

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_readbuf_watermark

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_readbuf_flip

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_intr_tpm_cmdaddr_notempty

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	60	3	3	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_ni))
-2-:	61	if (reg2hw_intr_test_qe_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T43,T122,T148
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Module : prim_intr_hw

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	19344	19344	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19344	19344	0	0
T1	12	12	0	0
T2	12	12	0	0
T3	12	12	0	0
T4	12	12	0	0
T5	12	12	0	0
T6	12	12	0	0
T7	12	12	0	0
T10	12	12	0	0
T11	12	12	0	0
T27	12	12	0	0

Line Coverage for Instance : tb.dut.u_intr_rxf

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
49	1	1
52	1	1
54	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_rxf

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T11
1	0	Covered	T122,T148,T149

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T43,T122,T148
1	1	Covered	T122,T148,T149

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T11

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T33,T8
1	0	Covered	T1,T2,T11
1	1	Covered	T33,T23,T26

---

Branch Coverage for Instance : tb.dut.u_intr_rxf

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_intr_rxf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1612	1612	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_rxlvl

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
49	1	1
52	1	1
54	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_rxlvl

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T43,T122,T148

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T43,T122,T148
1	1	Covered	T43,T122,T148

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T11,T33
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_intr_rxlvl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_intr_rxlvl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1612	1612	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_txlvl

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
49	1	1
52	1	1
54	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_txlvl

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T43,T122,T148

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T43,T122,T148
1	1	Covered	T43,T122,T148

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_intr_txlvl

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_intr_txlvl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1612	1612	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_rxerr

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
49	1	1
52	1	1
54	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_rxerr

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Unreachable
1	0	Covered	T43,T122,T148

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T43,T122,T148
1	1	Covered	T43,T122,T148

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T43,T122,T148
1	0	Covered	T43,T122,T148

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Covered	T43,T122,T148
1	1	Covered	T122,T148,T149

---

Branch Coverage for Instance : tb.dut.u_intr_rxerr

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_intr_rxerr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1612	1612	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_rxoverflow

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
49	1	1
52	1	1
54	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_rxoverflow

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T33,T23
1	0	Covered	T43,T122,T148

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T43,T122,T148
1	1	Covered	T43,T122,T148

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T2,T33,T23
1	0	Covered	T2,T33,T23

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T54,T150,T106
1	1	Covered	T2,T33,T23

---

Branch Coverage for Instance : tb.dut.u_intr_rxoverflow

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_intr_rxoverflow

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1612	1612	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_txunderflow

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
49	1	1
52	1	1
54	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_txunderflow

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T23,T39,T54
1	0	Covered	T43,T122,T148

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T43,T122,T148
1	1	Covered	T43,T122,T148

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T23,T39,T54
1	0	Covered	T23,T39,T54

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T39,T54
1	1	Covered	T23,T39,T54

---

Branch Coverage for Instance : tb.dut.u_intr_txunderflow

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_intr_txunderflow

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1612	1612	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_cmdfifo_not_empty

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
49	1	1
52	1	1
54	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_cmdfifo_not_empty

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T8
1	0	Covered	T43,T122,T148

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T43,T122,T148
1	1	Covered	T43,T122,T148

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T6,T7,T23
1	1	Covered	T8,T23,T43

---

Branch Coverage for Instance : tb.dut.u_intr_cmdfifo_not_empty

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_intr_cmdfifo_not_empty

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1612	1612	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_payload_not_empty

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
49	1	1
52	1	1
54	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_payload_not_empty

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T8
1	0	Covered	T43,T122,T148

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T43,T122,T148
1	1	Covered	T43,T122,T148

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T33,T23
1	0	Covered	T6,T7,T8
1	1	Covered	T23,T43,T122

---

Branch Coverage for Instance : tb.dut.u_intr_payload_not_empty

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_intr_payload_not_empty

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1612	1612	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_payload_overflow

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
49	1	1
52	1	1
54	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_payload_overflow

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T23
1	0	Covered	T43,T122,T148

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T43,T122,T148
1	1	Covered	T43,T122,T148

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T23
1	0	Covered	T6,T7,T23

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23
1	1	Covered	T43,T122,T62

---

Branch Coverage for Instance : tb.dut.u_intr_payload_overflow

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_intr_payload_overflow

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1612	1612	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_readbuf_watermark

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
49	1	1
52	1	1
54	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_readbuf_watermark

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T28,T31
1	0	Covered	T43,T122,T148

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T43,T122,T148
1	1	Covered	T43,T122,T148

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T28,T31
1	0	Covered	T9,T28,T31

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T8
1	0	Covered	T9,T28,T31
1	1	Covered	T43,T122,T148

---

Branch Coverage for Instance : tb.dut.u_intr_readbuf_watermark

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_intr_readbuf_watermark

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1612	1612	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_readbuf_flip

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
47	1	1
49	1	1
52	1	1
54	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_readbuf_flip

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T28,T31
1	0	Covered	T43,T122,T148

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T43,T122,T148
1	1	Covered	T43,T122,T148

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T9,T28,T31
1	0	Covered	T9,T28,T31

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T33
1	0	Covered	T9,T28,T31
1	1	Covered	T43,T122,T148

---

Branch Coverage for Instance : tb.dut.u_intr_readbuf_flip

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_intr_readbuf_flip

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1612	1612	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_intr_tpm_cmdaddr_notempty

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
ALWAYS	60	4	4	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
ALWAYS	80	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	2	2
61	2	2
			MISSING_ELSE
66	1	1
68	1	1
73	1	1
80	1	1
81	1	1
83	1	1

---

Cond Coverage for Instance : tb.dut.u_intr_tpm_cmdaddr_notempty

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T43,T122,T148
1	0	Covered	T7,T13,T8

 LINE       68
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T43,T122,T148
1	0	Covered	T7,T13,T8

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T13,T23
1	1	Covered	T8,T43,T122

---

Branch Coverage for Instance : tb.dut.u_intr_tpm_cmdaddr_notempty

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	60	3	3	100.00
IF	80	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_ni))
-2-:	61	if (reg2hw_intr_test_qe_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T43,T122,T148
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_intr_tpm_cmdaddr_notempty

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IntrTKind_A	1612	1612	0	0

IntrTKind_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0