Unified Coverage Report :: Module Instance :: tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

Module Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.85	100.00	65.38			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.96	100.00	65.38			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_fwmode_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.25	100.00	75.00			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	98.25	100.00		100.00	87.50	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	98.25	100.00		100.00	87.50	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.30	90.91	42.31			60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.72	85.00	42.31			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.89	77.78				50.00

Module Instance : tb.dut.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.77	100.00	73.08			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.85	95.00	73.08			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.29	96.97	80.53			91.67	100.00	u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.81	100.00	69.23			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.89	95.00	69.23			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.29	96.97	80.53			91.67	100.00	u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Module Instance : tb.dut.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.03	100.00	76.47			91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.12	95.00	76.47			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.29	96.97	80.53			91.67	100.00	u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.94	88.89				75.00

Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

	Total	Covered	Percent
Conditions	26	17	65.38
Logical	26	17	65.38
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T1,T5

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T2

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T1,T5

---

Branch Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T1,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T4,T1,T2
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1683556043	4806270	0	0
DepthKnown_A	1683556043	1648852944	0	0
RvalidKnown_A	1683556043	1648852944	0	0
WreadyKnown_A	1683556043	1648852944	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1683556043	4806270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	4806270	0	0
T1	137999	1534	0	0
T2	2112	12	0	0
T3	28540	81	0	0
T6	103085	0	0	0
T7	131277	0	0	0
T8	0	39830	0	0
T10	211932	0	0	0
T11	695382	2928	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T23	0	18245	0	0
T25	0	148	0	0
T26	0	2100	0	0
T33	2239	12	0	0
T37	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	1648852944	0	0
T1	137999	137999	0	0
T2	2112	2112	0	0
T3	28540	28540	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	695382	695382	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	1648852944	0	0
T1	137999	137999	0	0
T2	2112	2112	0	0
T3	28540	28540	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	695382	695382	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	1648852944	0	0
T1	137999	137999	0	0
T2	2112	2112	0	0
T3	28540	28540	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	695382	695382	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	4806270	0	0
T1	137999	1534	0	0
T2	2112	12	0	0
T3	28540	81	0	0
T6	103085	0	0	0
T7	131277	0	0	0
T8	0	39830	0	0
T10	211932	0	0	0
T11	695382	2928	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T23	0	18245	0	0
T25	0	148	0	0
T26	0	2100	0	0
T33	2239	12	0	0
T37	0	2	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	182	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
172	1	1
173	1	1
182	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	32	24	75.00
Logical	32	24	75.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T12

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T1,T5

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T12

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T7,T12
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T12

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T12
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T2

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Not Covered
1	1	Covered	T6,T7,T12

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T12

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T12

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T6,T7,T12

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T12
1	0	Covered	T6,T7,T12
1	1	Covered	T4,T1,T5

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	172	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T12
0	1	Covered	T4,T1,T5
0	0	Not Covered

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T4,T1,T2
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T12
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	397838743	23043274	0	0
DepthKnown_A	397838743	349859748	0	0
RvalidKnown_A	397838743	349859748	0	0
WreadyKnown_A	397838743	349859748	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	397838743	23043274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	23043274	0	0
T6	103085	151331	0	0
T7	131277	239610	0	0
T8	146466	18354	0	0
T9	13338	12220	0	0
T11	93697	0	0	0
T12	148629	50488	0	0
T13	122009	0	0	0
T14	0	225880	0	0
T15	0	30092	0	0
T23	114645	16904	0	0
T24	29758	0	0	0
T28	0	16924	0	0
T31	0	21302	0	0
T33	385	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	23043274	0	0
T6	103085	151331	0	0
T7	131277	239610	0	0
T8	146466	18354	0	0
T9	13338	12220	0	0
T11	93697	0	0	0
T12	148629	50488	0	0
T13	122009	0	0	0
T14	0	225880	0	0
T15	0	30092	0	0
T23	114645	16904	0	0
T24	29758	0	0	0
T28	0	16924	0	0
T31	0	21302	0	0
T33	385	0	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	182	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
172	1	1
173	1	1
182	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	32	28	87.50
Logical	32	28	87.50
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (2'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T12

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((2'(gen_normal_fifo.wptr_value) - 2'(gen_normal_fifo.rptr_value))) : (((2'(Depth) - 2'(gen_normal_fifo.rptr_value)) + 2'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T6,T7,T12
1	Covered	T4,T1,T5

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T6,T7,T12
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Covered	T6,T7,T12
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T12

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T7,T12
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T12

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T12
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T2

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Not Covered
1	1	Covered	T6,T7,T12

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T12

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T12

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T12
1	0	Covered	T4,T1,T5
1	1	Covered	T6,T7,T12

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T12
1	0	Covered	T6,T7,T12
1	1	Covered	T4,T1,T5

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	88	3	3	100.00
TERNARY	172	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T7,T12
0	1	Covered	T4,T1,T5
0	0	Covered	T6,T7,T12

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T12
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T4,T1,T2
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T12
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	397838743	24227023	0	0
DepthKnown_A	397838743	349859748	0	0
RvalidKnown_A	397838743	349859748	0	0
WreadyKnown_A	397838743	349859748	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	397838743	24227023	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	24227023	0	0
T6	103085	159075	0	0
T7	131277	252320	0	0
T8	146466	19606	0	0
T9	13338	13066	0	0
T11	93697	0	0	0
T12	148629	52112	0	0
T13	122009	0	0	0
T14	0	238791	0	0
T15	0	31147	0	0
T23	114645	17520	0	0
T24	29758	0	0	0
T28	0	17760	0	0
T31	0	22276	0	0
T33	385	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	24227023	0	0
T6	103085	159075	0	0
T7	131277	252320	0	0
T8	146466	19606	0	0
T9	13338	13066	0	0
T11	93697	0	0	0
T12	148629	52112	0	0
T13	122009	0	0	0
T14	0	238791	0	0
T15	0	31147	0	0
T23	114645	17520	0	0
T24	29758	0	0	0
T28	0	17760	0	0
T31	0	22276	0	0
T33	385	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	1	50.00
CONT_ASSIGN	175	1	0	0.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	0	1
			MISSING_ELSE
175	0	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	26	11	42.31
Logical	26	11	42.31
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T1,T5

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T2
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T2

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Not Covered
1	1	Not Covered

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T1,T5

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	88	3	1	33.33
TERNARY	180	2	1	50.00
IF	70	3	3	100.00
IF	165	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T1,T5
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T4,T1,T2
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	397838743	0	0	0
DepthKnown_A	397838743	349859748	0	0
RvalidKnown_A	397838743	349859748	0	0
WreadyKnown_A	397838743	349859748	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	397838743	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	26	19	73.08
Logical	26	19	73.08
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T1,T5

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T1,T2

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T10
1	1	0	Not Covered
1	1	1	Covered	T4,T1,T2

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Not Covered
1	1	Covered	T4,T1,T2

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T5

---

Branch Coverage for Instance : tb.dut.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T2
0	1	Covered	T4,T1,T5
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T4,T1,T5
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2066904029	22770769	0	0
DepthKnown_A	2066904029	2066769701	0	0
RvalidKnown_A	2066904029	2066769701	0	0
WreadyKnown_A	2066904029	2066769701	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2066904029	22770769	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	22770769	0	0
T1	138096	3068	0	0
T2	2220	12	0	0
T3	28636	722	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	120584	54821	0	0
T7	669057	20738	0	0
T9	0	1024	0	0
T10	79445	1024	0	0
T11	695390	5856	0	0
T12	0	1024	0	0
T27	1783	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	22770769	0	0
T1	138096	3068	0	0
T2	2220	12	0	0
T3	28636	722	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	120584	54821	0	0
T7	669057	20738	0	0
T9	0	1024	0	0
T10	79445	1024	0	0
T11	695390	5856	0	0
T12	0	1024	0	0
T27	1783	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	26	18	69.23
Logical	26	18	69.23
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T6

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T1,T5

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Not Covered
1	1	Covered	T1,T3,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T6

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T5

---

Branch Coverage for Instance : tb.dut.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T6
0	1	Covered	T4,T1,T5
0	0	Not Covered

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T4,T1,T5
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2066904029	5107794	0	0
DepthKnown_A	2066904029	2066769701	0	0
RvalidKnown_A	2066904029	2066769701	0	0
WreadyKnown_A	2066904029	2066769701	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2066904029	5107794	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	5107794	0	0
T1	138096	1534	0	0
T2	2220	0	0	0
T3	28636	81	0	0
T5	1257	0	0	0
T6	120584	641	0	0
T7	669057	258	0	0
T8	0	39831	0	0
T10	79445	0	0	0
T11	695390	2928	0	0
T12	104141	0	0	0
T14	0	321	0	0
T23	0	19766	0	0
T25	0	148	0	0
T26	0	2100	0	0
T27	1783	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	5107794	0	0
T1	138096	1534	0	0
T2	2220	0	0	0
T3	28636	81	0	0
T5	1257	0	0	0
T6	120584	641	0	0
T7	669057	258	0	0
T8	0	39831	0	0
T10	79445	0	0	0
T11	695390	2928	0	0
T12	104141	0	0	0
T14	0	321	0	0
T23	0	19766	0	0
T25	0	148	0	0
T26	0	2100	0	0
T27	1783	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	154	1	1	100.00
ALWAYS	157	2	2	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
154	1	1
157	1	1
158	1	1
			MISSING_ELSE
172	1	1
173	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	34	26	76.47
Logical	34	26	76.47
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (1'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T8

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((1'(gen_normal_fifo.wptr_value) - 1'(gen_normal_fifo.rptr_value))) : (((1'(Depth) - 1'(gen_normal_fifo.rptr_value)) + 1'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T1,T5

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T6
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Not Covered
1	1	Covered	T1,T3,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T3,T6,T8

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       172
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T6

 LINE       172
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T1,T3,T6

 LINE       173
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T3,T6
1	1	Covered	T4,T1,T5

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T5

---

Branch Coverage for Instance : tb.dut.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		12	11	91.67
TERNARY	88	3	2	66.67
TERNARY	172	2	2	100.00
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	157	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T6,T8
0	1	Covered	T4,T1,T5
0	0	Not Covered

	LineNo.	Expression
-1-:	172	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T4,T1,T5
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	157	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2066904029	9708954	0	0
DepthKnown_A	2066904029	2066769701	0	0
RvalidKnown_A	2066904029	2066769701	0	0
WreadyKnown_A	2066904029	2066769701	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2066904029	9708954	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	9708954	0	0
T1	138096	1534	0	0
T2	2220	0	0	0
T3	28636	377	0	0
T5	1257	0	0	0
T6	120584	2845	0	0
T7	669057	258	0	0
T8	0	39834	0	0
T10	79445	0	0	0
T11	695390	2928	0	0
T12	104141	0	0	0
T14	0	321	0	0
T23	0	19766	0	0
T25	0	650	0	0
T26	0	6575	0	0
T27	1783	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	9708954	0	0
T1	138096	1534	0	0
T2	2220	0	0	0
T3	28636	377	0	0
T5	1257	0	0	0
T6	120584	2845	0	0
T7	669057	258	0	0
T8	0	39834	0	0
T10	79445	0	0	0
T11	695390	2928	0	0
T12	104141	0	0	0
T14	0	321	0	0
T23	0	19766	0	0
T25	0	650	0	0
T26	0	6575	0	0
T27	1783	0	0	0