Unified Coverage Report :: Module Instance :: tb.dut.u_sys_sram_arbiter.u_req_fifo

Module Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.85	100.00	65.38			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.96	100.00	65.38			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	26	17	65.38
Logical	26	17	65.38
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T5

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Not Covered
1	1	Covered	T1,T3,T6

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T5

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T4,T1,T5
0	0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T4,T1,T5
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2066904029	5111250	0	0
DepthKnown_A	2066904029	2066769701	0	0
RvalidKnown_A	2066904029	2066769701	0	0
WreadyKnown_A	2066904029	2066769701	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2066904029	5111250	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	5111250	0	0
T1	138096	1534	0	0
T2	2220	0	0	0
T3	28636	81	0	0
T5	1257	0	0	0
T6	120584	677	0	0
T7	669057	302	0	0
T8	0	39833	0	0
T10	79445	0	0	0
T11	695390	2928	0	0
T12	104141	0	0	0
T14	0	357	0	0
T23	0	19780	0	0
T25	0	148	0	0
T26	0	2100	0	0
T27	1783	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	5111250	0	0
T1	138096	1534	0	0
T2	2220	0	0	0
T3	28636	81	0	0
T5	1257	0	0	0
T6	120584	677	0	0
T7	669057	302	0	0
T8	0	39833	0	0
T10	79445	0	0	0
T11	695390	2928	0	0
T12	104141	0	0	0
T14	0	357	0	0
T23	0	19780	0	0
T25	0	148	0	0
T26	0	2100	0	0
T27	1783	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2069240229	255233991	0	0
DepthKnown_A	2069240229	2069063742	0	0
RvalidKnown_A	2069240229	2069063742	0	0
WreadyKnown_A	2069240229	2069063742	0	0
gen_passthru_fifo.paramCheckPass	1786	1786	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	255233991	0	0
T1	138096	10601	0	0
T2	2220	39	0	0
T3	28636	471	0	0
T4	912522	1115	0	0
T5	1257	22	0	0
T6	120584	37296	0	0
T7	669057	131367	0	0
T10	79445	2140	0	0
T11	695390	279611	0	0
T27	1783	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786	1786	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2069240229	280270213	0	0
DepthKnown_A	2069240229	2069063742	0	0
RvalidKnown_A	2069240229	2069063742	0	0
WreadyKnown_A	2069240229	2069063742	0	0
gen_passthru_fifo.paramCheckPass	1786	1786	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	280270213	0	0
T1	138096	9776	0	0
T2	2220	39	0	0
T3	28636	2189	0	0
T4	912522	1115	0	0
T5	1257	22	0	0
T6	120584	112493	0	0
T7	669057	118578	0	0
T10	79445	1117	0	0
T11	695390	231380	0	0
T27	1783	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786	1786	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2069240229	13915323	0	0
DepthKnown_A	2069240229	2069063742	0	0
RvalidKnown_A	2069240229	2069063742	0	0
WreadyKnown_A	2069240229	2069063742	0	0
gen_passthru_fifo.paramCheckPass	1786	1786	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	13915323	0	0
T1	138096	3068	0	0
T2	2220	12	0	0
T3	28636	162	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	120584	21126	0	0
T7	669057	33014	0	0
T10	79445	2047	0	0
T11	695390	5877	0	0
T12	0	1024	0	0
T27	1783	0	0	0
T56	0	178	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786	1786	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2069240229	22865797	0	0
DepthKnown_A	2069240229	2069063742	0	0
RvalidKnown_A	2069240229	2069063742	0	0
WreadyKnown_A	2069240229	2069063742	0	0
gen_passthru_fifo.paramCheckPass	1786	1786	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	22865797	0	0
T1	138096	3068	0	0
T2	2220	12	0	0
T3	28636	722	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	120584	54821	0	0
T7	669057	20738	0	0
T10	79445	1024	0	0
T11	695390	5856	0	0
T12	0	1024	0	0
T27	1783	0	0	0
T56	0	168	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786	1786	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2069240229	236637390	0	0
DepthKnown_A	2069240229	2069063742	0	0
RvalidKnown_A	2069240229	2069063742	0	0
WreadyKnown_A	2069240229	2069063742	0	0
gen_passthru_fifo.paramCheckPass	1786	1786	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	236637390	0	0
T1	138096	6756	0	0
T2	2220	27	0	0
T3	28636	309	0	0
T4	912522	91	0	0
T5	1257	22	0	0
T6	120584	13284	0	0
T7	669057	98159	0	0
T10	79445	93	0	0
T11	695390	278465	0	0
T27	1783	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786	1786	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2069240229	257404416	0	0
DepthKnown_A	2069240229	2069063742	0	0
RvalidKnown_A	2069240229	2069063742	0	0
WreadyKnown_A	2069240229	2069063742	0	0
gen_passthru_fifo.paramCheckPass	1786	1786	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	257404416	0	0
T1	138096	6708	0	0
T2	2220	27	0	0
T3	28636	1467	0	0
T4	912522	91	0	0
T5	1257	22	0	0
T6	120584	57672	0	0
T7	669057	97840	0	0
T10	79445	93	0	0
T11	695390	230794	0	0
T27	1783	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2069240229	2069063742	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786	1786	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0