Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_fwmode_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.53	100.00

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T2

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T4,T1,T2

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T4,T1,T2
0	0	1	Unreachable
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T5

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	4836	4836	0	0
GntImpliesReady_A	2147483647	22570381	0	0
GntImpliesValid_A	2147483647	22570381	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	22570381	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	0	0	0
ReadyAndValidImplyGrant_A	2147483647	22570381	0	0
ReqAndReadyImplyGrant_A	2147483647	22570381	0	0
ReqImpliesValid_A	2147483647	22570381	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	878	0	2341
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	22570381	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	325184	325106	0	0
T2	4717	4625	0	0
T3	60089	60003	0	0
T4	1365870	1365073	0	0
T5	1257	1173	0	0
T6	326754	326007	0	0
T7	931611	925160	0	0
T9	0	26676	0	0
T10	503309	502267	0	0
T11	1484469	1484461	0	0
T12	297258	296444	0	0
T13	244018	0	0	0
T27	1783	1703	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4836	4836	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T10	3	3	0	0
T11	3	3	0	0
T27	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22570381	0	0
T1	276095	6136	0	0
T2	4332	31	0	0
T3	57176	324	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	326754	26034	0	0
T7	931611	26911	0	0
T8	146466	79666	0	0
T9	0	1024	0	0
T10	291377	1024	0	0
T11	1484469	11712	0	0
T12	297258	1024	0	0
T13	244018	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	38874	0	0
T24	29758	0	0	0
T25	4737	527	0	0
T26	67201	4200	0	0
T27	1783	0	0	0
T33	2239	21	0	0
T37	0	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22570381	0	0
T1	276095	6136	0	0
T2	4332	31	0	0
T3	57176	324	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	326754	26034	0	0
T7	931611	26911	0	0
T8	146466	79666	0	0
T9	0	1024	0	0
T10	291377	1024	0	0
T11	1484469	11712	0	0
T12	297258	1024	0	0
T13	244018	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	38874	0	0
T24	29758	0	0	0
T25	4737	527	0	0
T26	67201	4200	0	0
T27	1783	0	0	0
T33	2239	21	0	0
T37	0	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	325184	325106	0	0
T2	4717	4625	0	0
T3	60089	60003	0	0
T4	1365870	1365073	0	0
T5	1257	1173	0	0
T6	326754	326007	0	0
T7	931611	925160	0	0
T9	0	26676	0	0
T10	503309	502267	0	0
T11	1484469	1484461	0	0
T12	297258	296444	0	0
T13	244018	0	0	0
T27	1783	1703	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	325184	325106	0	0
T2	4717	4625	0	0
T3	60089	60003	0	0
T4	1365870	1365073	0	0
T5	1257	1173	0	0
T6	326754	326007	0	0
T7	931611	925160	0	0
T9	0	26676	0	0
T10	503309	502267	0	0
T11	1484469	1484461	0	0
T12	297258	296444	0	0
T13	244018	0	0	0
T27	1783	1703	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22570381	0	0
T1	276095	6136	0	0
T2	4332	31	0	0
T3	57176	324	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	326754	26034	0	0
T7	931611	26911	0	0
T8	146466	79666	0	0
T9	0	1024	0	0
T10	291377	1024	0	0
T11	1484469	11712	0	0
T12	297258	1024	0	0
T13	244018	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	38874	0	0
T24	29758	0	0	0
T25	4737	527	0	0
T26	67201	4200	0	0
T27	1783	0	0	0
T33	2239	21	0	0
T37	0	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22570381	0	0
T1	276095	6136	0	0
T2	4332	31	0	0
T3	57176	324	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	326754	26034	0	0
T7	931611	26911	0	0
T8	146466	79666	0	0
T9	0	1024	0	0
T10	291377	1024	0	0
T11	1484469	11712	0	0
T12	297258	1024	0	0
T13	244018	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	38874	0	0
T24	29758	0	0	0
T25	4737	527	0	0
T26	67201	4200	0	0
T27	1783	0	0	0
T33	2239	21	0	0
T37	0	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22570381	0	0
T1	276095	6136	0	0
T2	4332	31	0	0
T3	57176	324	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	326754	26034	0	0
T7	931611	26911	0	0
T8	146466	79666	0	0
T9	0	1024	0	0
T10	291377	1024	0	0
T11	1484469	11712	0	0
T12	297258	1024	0	0
T13	244018	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	38874	0	0
T24	29758	0	0	0
T25	4737	527	0	0
T26	67201	4200	0	0
T27	1783	0	0	0
T33	2239	21	0	0
T37	0	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22570381	0	0
T1	276095	6136	0	0
T2	4332	31	0	0
T3	57176	324	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	326754	26034	0	0
T7	931611	26911	0	0
T8	146466	79666	0	0
T9	0	1024	0	0
T10	291377	1024	0	0
T11	1484469	11712	0	0
T12	297258	1024	0	0
T13	244018	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	38874	0	0
T24	29758	0	0	0
T25	4737	527	0	0
T26	67201	4200	0	0
T27	1783	0	0	0
T33	2239	21	0	0
T37	0	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	878	0	2341
T15	535309	0	0	0
T18	129591	0	0	0
T19	0	0	0	0
T28	18040	0	0	0
T29	0	0	0	0
T38	511170	8	0	1
T39	233887	3	0	1
T40	558508	1	0	1
T41	216915	1	0	1
T42	0	1	0	0
T43	0	1	0	0
T44	0	7	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	17	0	0
T48	143241	0	0	1
T49	1377	0	0	1
T50	24668	0	0	1
T51	0	0	0	0
T52	0	0	0	0
T53	0	0	0	1
T54	0	0	0	1
T55	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	325184	325106	0	0
T2	4717	4625	0	0
T3	60089	60003	0	0
T4	1365870	1365073	0	0
T5	1257	1173	0	0
T6	326754	326007	0	0
T7	931611	925160	0	0
T9	0	26676	0	0
T10	503309	502267	0	0
T11	1484469	1484461	0	0
T12	297258	296444	0	0
T13	244018	0	0	0
T27	1783	1703	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22570381	0	0
T1	276095	6136	0	0
T2	4332	31	0	0
T3	57176	324	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	326754	26034	0	0
T7	931611	26911	0	0
T8	146466	79666	0	0
T9	0	1024	0	0
T10	291377	1024	0	0
T11	1484469	11712	0	0
T12	297258	1024	0	0
T13	244018	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	38874	0	0
T24	29758	0	0	0
T25	4737	527	0	0
T26	67201	4200	0	0
T27	1783	0	0	0
T33	2239	21	0	0
T37	0	3	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T8
1	0	Covered	T6,T7,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T6,T7,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T6,T7,T8
0	0	1	Unreachable
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	397838743	349859748	0	0
CheckNGreaterZero_A	1612	1612	0	0
GntImpliesReady_A	397838743	508244	0	0
GntImpliesValid_A	397838743	508244	0	0
GrantKnown_A	397838743	349859748	0	0
IdxKnown_A	397838743	349859748	0	0
IndexIsCorrect_A	397838743	508244	0	0
LockArbDecision_A	397838743	0	0	0
NoReadyValidNoGrant_A	397838743	0	0	0
ReadyAndValidImplyGrant_A	397838743	508244	0	0
ReqAndReadyImplyGrant_A	397838743	508244	0	0
ReqImpliesValid_A	397838743	508244	0	0
ReqStaysHighUntilGranted0_M	397838743	0	0	0
RoundRobin_A	397838743	0	0	0
ValidKnown_A	397838743	349859748	0	0
gen_data_port_assertion.DataFlow_A	397838743	508244	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	508244	0	0
T6	103085	9997	0	0
T7	131277	6129	0	0
T8	146466	6	0	0
T11	93697	0	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	1059	0	0
T24	29758	0	0	0
T25	4737	0	0	0
T26	67201	0	0	0
T29	0	1564	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	508244	0	0
T6	103085	9997	0	0
T7	131277	6129	0	0
T8	146466	6	0	0
T11	93697	0	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	1059	0	0
T24	29758	0	0	0
T25	4737	0	0	0
T26	67201	0	0	0
T29	0	1564	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	508244	0	0
T6	103085	9997	0	0
T7	131277	6129	0	0
T8	146466	6	0	0
T11	93697	0	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	1059	0	0
T24	29758	0	0	0
T25	4737	0	0	0
T26	67201	0	0	0
T29	0	1564	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	508244	0	0
T6	103085	9997	0	0
T7	131277	6129	0	0
T8	146466	6	0	0
T11	93697	0	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	1059	0	0
T24	29758	0	0	0
T25	4737	0	0	0
T26	67201	0	0	0
T29	0	1564	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	508244	0	0
T6	103085	9997	0	0
T7	131277	6129	0	0
T8	146466	6	0	0
T11	93697	0	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	1059	0	0
T24	29758	0	0	0
T25	4737	0	0	0
T26	67201	0	0	0
T29	0	1564	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	508244	0	0
T6	103085	9997	0	0
T7	131277	6129	0	0
T8	146466	6	0	0
T11	93697	0	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	1059	0	0
T24	29758	0	0	0
T25	4737	0	0	0
T26	67201	0	0	0
T29	0	1564	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	508244	0	0
T6	103085	9997	0	0
T7	131277	6129	0	0
T8	146466	6	0	0
T11	93697	0	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T14	0	3124	0	0
T15	0	132	0	0
T16	0	3739	0	0
T18	0	14566	0	0
T19	0	10975	0	0
T23	114645	1059	0	0
T24	29758	0	0	0
T25	4737	0	0	0
T26	67201	0	0	0
T29	0	1564	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T6,T7,T8
1	0	Covered	T4,T1,T2

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T4,T1,T2

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T4,T1,T2
0	0	1	Unreachable
0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2066904029	2066769701	0	0
CheckNGreaterZero_A	1612	1612	0	0
GntImpliesReady_A	2066904029	12181327	0	0
GntImpliesValid_A	2066904029	12181327	0	0
GrantKnown_A	2066904029	2066769701	0	0
IdxKnown_A	2066904029	2066769701	0	0
IndexIsCorrect_A	2066904029	12181327	0	0
LockArbDecision_A	2066904029	0	0	0
NoReadyValidNoGrant_A	2066904029	0	0	0
ReadyAndValidImplyGrant_A	2066904029	12181327	0	0
ReqAndReadyImplyGrant_A	2066904029	12181327	0	0
ReqImpliesValid_A	2066904029	12181327	0	0
ReqStaysHighUntilGranted0_M	2066904029	0	0	0
RoundRobin_A	2066904029	0	0	1612
ValidKnown_A	2066904029	2066769701	0	0
gen_data_port_assertion.DataFlow_A	2066904029	12181327	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	12181327	0	0
T1	138096	3068	0	0
T2	2220	12	0	0
T3	28636	162	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	120584	16037	0	0
T7	669057	20782	0	0
T9	0	1024	0	0
T10	79445	1024	0	0
T11	695390	5856	0	0
T12	0	1024	0	0
T27	1783	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	12181327	0	0
T1	138096	3068	0	0
T2	2220	12	0	0
T3	28636	162	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	120584	16037	0	0
T7	669057	20782	0	0
T9	0	1024	0	0
T10	79445	1024	0	0
T11	695390	5856	0	0
T12	0	1024	0	0
T27	1783	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	12181327	0	0
T1	138096	3068	0	0
T2	2220	12	0	0
T3	28636	162	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	120584	16037	0	0
T7	669057	20782	0	0
T9	0	1024	0	0
T10	79445	1024	0	0
T11	695390	5856	0	0
T12	0	1024	0	0
T27	1783	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	12181327	0	0
T1	138096	3068	0	0
T2	2220	12	0	0
T3	28636	162	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	120584	16037	0	0
T7	669057	20782	0	0
T9	0	1024	0	0
T10	79445	1024	0	0
T11	695390	5856	0	0
T12	0	1024	0	0
T27	1783	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	12181327	0	0
T1	138096	3068	0	0
T2	2220	12	0	0
T3	28636	162	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	120584	16037	0	0
T7	669057	20782	0	0
T9	0	1024	0	0
T10	79445	1024	0	0
T11	695390	5856	0	0
T12	0	1024	0	0
T27	1783	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	12181327	0	0
T1	138096	3068	0	0
T2	2220	12	0	0
T3	28636	162	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	120584	16037	0	0
T7	669057	20782	0	0
T9	0	1024	0	0
T10	79445	1024	0	0
T11	695390	5856	0	0
T12	0	1024	0	0
T27	1783	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	0	0	1612

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	2066769701	0	0
T1	138096	138019	0	0
T2	2220	2129	0	0
T3	28636	28559	0	0
T4	912522	912433	0	0
T5	1257	1173	0	0
T6	120584	120575	0	0
T7	669057	669050	0	0
T10	79445	79355	0	0
T11	695390	695383	0	0
T27	1783	1703	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2066904029	12181327	0	0
T1	138096	3068	0	0
T2	2220	12	0	0
T3	28636	162	0	0
T4	912522	1024	0	0
T5	1257	0	0	0
T6	120584	16037	0	0
T7	669057	20782	0	0
T9	0	1024	0	0
T10	79445	1024	0	0
T11	695390	5856	0	0
T12	0	1024	0	0
T27	1783	0	0	0

Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T1,T5

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1683556043	1648852944	0	0
CheckNGreaterZero_A	1612	1612	0	0
GntImpliesReady_A	1683556043	9880810	0	0
GntImpliesValid_A	1683556043	9880810	0	0
GrantKnown_A	1683556043	1648852944	0	0
IdxKnown_A	1683556043	1648852944	0	0
IndexIsCorrect_A	1683556043	9880810	0	0
LockArbDecision_A	1683556043	0	0	0
NoReadyValidNoGrant_A	1683556043	0	0	0
ReadyAndValidImplyGrant_A	1683556043	9880810	0	0
ReqAndReadyImplyGrant_A	1683556043	9880810	0	0
ReqImpliesValid_A	1683556043	9880810	0	0
ReqStaysHighUntilGranted0_M	1683556043	0	0	0
RoundRobin_A	1683556043	878	0	729
ValidKnown_A	1683556043	1648852944	0	0
gen_data_port_assertion.DataFlow_A	1683556043	9880810	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	1648852944	0	0
T1	137999	137999	0	0
T2	2112	2112	0	0
T3	28540	28540	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	695382	695382	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1612	1612	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T27	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	9880810	0	0
T1	137999	3068	0	0
T2	2112	19	0	0
T3	28540	162	0	0
T6	103085	0	0	0
T7	131277	0	0	0
T8	0	79660	0	0
T10	211932	0	0	0
T11	695382	5856	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T23	0	37815	0	0
T25	0	527	0	0
T26	0	4200	0	0
T33	2239	21	0	0
T37	0	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	9880810	0	0
T1	137999	3068	0	0
T2	2112	19	0	0
T3	28540	162	0	0
T6	103085	0	0	0
T7	131277	0	0	0
T8	0	79660	0	0
T10	211932	0	0	0
T11	695382	5856	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T23	0	37815	0	0
T25	0	527	0	0
T26	0	4200	0	0
T33	2239	21	0	0
T37	0	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	1648852944	0	0
T1	137999	137999	0	0
T2	2112	2112	0	0
T3	28540	28540	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	695382	695382	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	1648852944	0	0
T1	137999	137999	0	0
T2	2112	2112	0	0
T3	28540	28540	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	695382	695382	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	9880810	0	0
T1	137999	3068	0	0
T2	2112	19	0	0
T3	28540	162	0	0
T6	103085	0	0	0
T7	131277	0	0	0
T8	0	79660	0	0
T10	211932	0	0	0
T11	695382	5856	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T23	0	37815	0	0
T25	0	527	0	0
T26	0	4200	0	0
T33	2239	21	0	0
T37	0	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	9880810	0	0
T1	137999	3068	0	0
T2	2112	19	0	0
T3	28540	162	0	0
T6	103085	0	0	0
T7	131277	0	0	0
T8	0	79660	0	0
T10	211932	0	0	0
T11	695382	5856	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T23	0	37815	0	0
T25	0	527	0	0
T26	0	4200	0	0
T33	2239	21	0	0
T37	0	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	9880810	0	0
T1	137999	3068	0	0
T2	2112	19	0	0
T3	28540	162	0	0
T6	103085	0	0	0
T7	131277	0	0	0
T8	0	79660	0	0
T10	211932	0	0	0
T11	695382	5856	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T23	0	37815	0	0
T25	0	527	0	0
T26	0	4200	0	0
T33	2239	21	0	0
T37	0	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	9880810	0	0
T1	137999	3068	0	0
T2	2112	19	0	0
T3	28540	162	0	0
T6	103085	0	0	0
T7	131277	0	0	0
T8	0	79660	0	0
T10	211932	0	0	0
T11	695382	5856	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T23	0	37815	0	0
T25	0	527	0	0
T26	0	4200	0	0
T33	2239	21	0	0
T37	0	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	878	0	729
T15	535309	0	0	0
T18	129591	0	0	0
T19	0	0	0	0
T28	18040	0	0	0
T29	0	0	0	0
T38	511170	8	0	1
T39	233887	3	0	1
T40	558508	1	0	1
T41	216915	1	0	1
T42	0	1	0	0
T43	0	1	0	0
T44	0	7	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	17	0	0
T48	143241	0	0	1
T49	1377	0	0	1
T50	24668	0	0	1
T51	0	0	0	0
T52	0	0	0	0
T53	0	0	0	1
T54	0	0	0	1
T55	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	1648852944	0	0
T1	137999	137999	0	0
T2	2112	2112	0	0
T3	28540	28540	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	695382	695382	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683556043	9880810	0	0
T1	137999	3068	0	0
T2	2112	19	0	0
T3	28540	162	0	0
T6	103085	0	0	0
T7	131277	0	0	0
T8	0	79660	0	0
T10	211932	0	0	0
T11	695382	5856	0	0
T12	148629	0	0	0
T13	122009	0	0	0
T23	0	37815	0	0
T25	0	527	0	0
T26	0	4200	0	0
T33	2239	21	0	0
T37	0	3	0	0