Unified Coverage Report :: Module :: spi_readcmd

Module : spi_readcmd

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	96.32	100.00		80.00	84.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_readcmd	92.19	96.32	100.00		80.00	84.62	100.00

---

Module Instance : tb.dut.u_readcmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	96.32	100.00		80.00	84.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.14	97.16	93.19		87.50	87.82	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_addr_latch_pulse	100.00	100.00	100.00			100.00
u_readbuffer	96.23	97.30	97.14			90.48	100.00
u_readsram	94.65	97.81	85.71		100.00	89.71	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_readcmd

	Line No.	Total	Covered	Percent
TOTAL		136	131	96.32
CONT_ASSIGN	179	1	1	100.00
CONT_ASSIGN	182	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
ALWAYS	348	4	4	100.00
ALWAYS	364	4	4	100.00
CONT_ASSIGN	373	1	1	100.00
ALWAYS	376	12	12	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
ALWAYS	422	3	3	100.00
ALWAYS	430	7	7	100.00
ALWAYS	451	6	6	100.00
CONT_ASSIGN	460	1	1	100.00
ALWAYS	464	12	12	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	495	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
ALWAYS	508	8	8	100.00
CONT_ASSIGN	524	1	1	100.00
ALWAYS	529	5	5	100.00
ALWAYS	547	4	4	100.00
CONT_ASSIGN	560	1	1	100.00
ALWAYS	570	3	3	100.00
ALWAYS	578	48	43	89.58
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	716	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
179	1	1
182	1	1
185	1	1
188	1	1
328	1	1
335	1	1
348	1	1
349	1	1
350	1	1
351	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
369	1	1
			MISSING_ELSE
373	1	1
376	1	1
377	1	1
379	1	1
381	1	1
382	1	1
385	1	1
386	1	1
388	1	1
389	1	1
390	1	1
392	1	1
393	1	1
			MISSING_ELSE
399	1	1
400	1	1
403	1	1
419	1	1
422	1	1
423	1	1
425	1	1
430	1	1
431	1	1
438	1	1
440	1	1
441	1	1
442	1	1
444	1	1
			==> MISSING_ELSE
451	1	1
452	1	1
453	1	1
455	1	1
456	1	1
457	1	1
			MISSING_ELSE
460	1	1
464	1	1
465	1	1
466	1	1
467	1	1
468	1	1
469	1	1
470	1	1
473	1	1
474	1	1
475	1	1
476	1	1
477	1	1
			MISSING_ELSE
491	1	1
492	1	1
495	1	1
496	1	1
508	2	2
509	1	1
511	1	1
512	1	1
515	1	1
516	1	1
518	1	1
			MISSING_ELSE
524	1	1
529	1	1
530	1	1
531	1	1
533	1	1
534	1	1
547	1	1
548	1	1
549	1	1
555	1	1
			MISSING_ELSE
560	1	1
570	1	1
571	1	1
573	1	1
578	1	1
580	1	1
583	1	1
584	1	1
585	1	1
586	1	1
588	1	1
589	1	1
591	1	1
592	1	1
594	1	1
596	1	1
597	1	1
599	1	1
601	1	1
604	1	1
606	1	1
			MISSING_ELSE
611	1	1
613	1	1
614	1	1
			MISSING_ELSE
617	1	1
620	1	1
626	1	1
629	1	1
630	1	1
631	1	1
636	1	1
638	1	1
643	0	1
			MISSING_ELSE
654	0	1
655	0	1
657	0	1
			==> MISSING_ELSE
662	1	1
663	1	1
664	1	1
665	1	1
			MISSING_ELSE
670	1	1
674	1	1
679	1	1
680	1	1
681	1	1
682	1	1
686	1	1
688	1	1
691	1	1
694	1	1
695	1	1
			MISSING_ELSE
700	0	1
715	1	1
716	1	1

---

Cond Coverage for Module : spi_readcmd

	Total	Covered	Percent
Conditions	66	66	100.00
Logical	66	66	100.00
Non-Logical	0	0
Event	0	0

 LINE       328
 EXPRESSION (sel_dp_i == DpReadSFDP)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T23

 LINE       335
 EXPRESSION (spi_mode_i == FlashMode)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       366
 EXPRESSION ((main_st == MainOutput) && (sel_dp_i == DpReadCmd) && addr_latch_en && ( ! (mailbox_en_i && addr_q_in_mailbox) ) && spid_in_flashmode)
             -----------1-----------    -----------2-----------    ------3------    --------------------4--------------------    --------5--------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	1	1	1	1	Covered	T9,T23,T28
1	0	1	1	1	Covered	T23,T29,T30
1	1	0	1	1	Covered	T9,T28,T31
1	1	1	0	1	Covered	T23,T32,T29
1	1	1	1	0	Covered	T6,T7,T12
1	1	1	1	1	Covered	T9,T28,T31

 LINE       366
 SUB-EXPRESSION (main_st == MainOutput)
                -----------1-----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T7,T12

 LINE       366
 SUB-EXPRESSION (sel_dp_i == DpReadCmd)
                -----------1-----------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T7,T12

 LINE       366
 SUB-EXPRESSION ( ! (mailbox_en_i && addr_q_in_mailbox) )
                    -----------------1-----------------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T6,T7,T12

 LINE       366
 SUB-EXPRESSION (mailbox_en_i && addr_q_in_mailbox)
                 ------1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T10,T6
1	1	Covered	T6,T7,T12

 LINE       386
 EXPRESSION (addr_shift_en && s2p_valid_i)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T6,T7,T12
1	1	Covered	T6,T7,T12

 LINE       399
 EXPRESSION (addr_cnt_d == 5'd2)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T12

 LINE       400
 EXPRESSION (addr_cnt_d == 5'b1)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T12

 LINE       403
 EXPRESSION (addr_cnt_d == 5'b0)
            ----------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       438
 EXPRESSION ((cmdinfo_addr_mode == Addr4B) ? 5'd31 : 5'd23)
             --------------1--------------

-1-	Status	Tests
0	Covered	T6,T7,T9
1	Covered	T6,T7,T12

 LINE       438
 SUB-EXPRESSION (cmdinfo_addr_mode == Addr4B)
                --------------1--------------

-1-	Status	Tests
0	Covered	T6,T7,T9
1	Covered	T6,T7,T12

 LINE       440
 EXPRESSION (addr_cnt_q == '0)
            ---------1--------

-1-	Status	Tests
0	Covered	T6,T7,T12
1	Covered	T4,T1,T5

 LINE       495
 EXPRESSION (mailbox_masked_addr_d == mailbox_addr_i)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       496
 EXPRESSION (mailbox_masked_addr_q == mailbox_addr_i)
            --------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       509
 EXPRESSION (sram_req && mailbox_en_i && cfg_intercept_en_mbx_i && addr_d_in_mailbox)
             ----1---    ------2-----    -----------3----------    --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T6,T7,T23
1	0	1	1	Covered	T6,T7,T8
1	1	0	1	Covered	T6,T7,T23
1	1	1	0	Covered	T6,T7,T8
1	1	1	1	Covered	T6,T7,T23

 LINE       512
 EXPRESSION (mailbox_en_i && cfg_intercept_en_mbx_i && addr_d_in_mailbox && (bitcnt == 3'b0))
             ------1-----    -----------2----------    --------3--------    --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T6,T7,T8
1	0	1	1	Covered	T6,T7,T12
1	1	0	1	Covered	T4,T10,T6
1	1	1	0	Covered	T6,T7,T23
1	1	1	1	Covered	T6,T7,T23

 LINE       512
 SUB-EXPRESSION (bitcnt == 3'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T6,T7,T12
1	Covered	T4,T1,T2

 LINE       516
 EXPRESSION (((!addr_d_in_mailbox)) && (bitcnt == 3'b0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T12
1	1	Covered	T4,T10,T6

 LINE       516
 SUB-EXPRESSION (bitcnt == 3'b0)
                --------1-------

-1-	Status	Tests
0	Covered	T6,T7,T12
1	Covered	T4,T1,T2

 LINE       560
 EXPRESSION ((main_st == MainOutput) && (addr_q[9:0] == '1))
             -----------1-----------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T9
1	0	Covered	T6,T7,T12
1	1	Covered	T6,T7,T12

 LINE       560
 SUB-EXPRESSION (main_st == MainOutput)
                -----------1-----------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T12

 LINE       560
 SUB-EXPRESSION (addr_q[9:0] == '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T12

 LINE       686
 EXPRESSION (bitcnt == 3'b0)
            --------1-------

-1-	Status	Tests
0	Covered	T6,T7,T12
1	Covered	T6,T7,T12

 LINE       729
 EXPRESSION (sel_dp_i == DpReadSFDP)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T6,T7,T23

---

FSM Coverage for Module : spi_readcmd

Summary for FSM :: main_st

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	5	4	80.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: main_st

---

states	Line No.	Covered	Tests
MainAddress	604	Covered	T6,T7,T12
MainDummy	636	Covered	T6,T7,T9
MainError	647	Not Covered
MainMByte	643	Excluded
MainOutput	629	Covered	T6,T7,T12
MainReset	600	Covered	T4,T1,T5

transitions	Line No.	Covered	Tests
MainAddress->MainDummy	636	Covered	T6,T7,T9
MainAddress->MainError	647	Not Covered
MainAddress->MainMByte	643	Excluded
MainAddress->MainOutput	629	Covered	T6,T7,T12
MainDummy->MainOutput	663	Covered	T6,T7,T9
MainMByte->MainDummy	655	Excluded
MainReset->MainAddress	604	Covered	T6,T7,T12

---

Branch Coverage for Module : spi_readcmd

	Line No.	Total	Covered	Percent
Branches		65	55	84.62
IF	348	3	3	100.00
IF	364	3	3	100.00
IF	379	5	5	100.00
IF	422	2	2	100.00
IF	431	5	4	80.00
IF	451	4	4	100.00
IF	464	10	8	80.00
IF	508	5	5	100.00
IF	529	2	2	100.00
IF	547	3	3	100.00
IF	570	2	2	100.00
CASE	599	21	14	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_readcmd.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	if ((!rst_ni))
-2-:	350	if (addr_latch_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T6,T7,T12
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	364	if ((!sys_rst_ni))
-2-:	366	if ((((((main_st == MainOutput) && (sel_dp_i == DpReadCmd)) && addr_latch_en) && (!(mailbox_en_i && addr_q_in_mailbox))) && spid_in_flashmode))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T9,T28,T31
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	379	if (addr_ready_in_word)
-2-:	382	if (addr_ready_in_halfword)
-3-:	386	if ((addr_shift_en && s2p_valid_i))
-4-:	390	if (addr_inc)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T6,T7,T12
0	1	-	-	Covered	T6,T7,T12
0	0	1	-	Covered	T6,T7,T12
0	0	0	1	Covered	T6,T7,T12
0	0	0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	422	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	431	if (addr_cnt_set)
-2-:	438	((cmdinfo_addr_mode == Addr4B)) ? 
-3-:	440	if ((addr_cnt_q == '0))
-4-:	442	if (addr_shift_en)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T6,T7,T12
1	0	-	-	Covered	T6,T7,T9
0	-	1	-	Covered	T4,T1,T5
0	-	0	1	Covered	T6,T7,T12
0	-	0	0	Not Covered

	LineNo.	Expression
-1-:	451	if ((!rst_ni))
-2-:	453	if (load_dummycnt)
-3-:	456	if ((!dummycnt_eq_zero))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T1,T5
0	1	-	Covered	T6,T7,T9
0	0	1	Covered	T6,T7,T9
0	0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	466	if (bitcnt_update)
-3-:	467	case (cmd_info_i.payload_en)
-4-:	473	if (bitcnt_dec)
-5-:	474	case (cmd_info_i.payload_en)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T1,T5
0	1	4'b0010	-	-	Covered	T6,T7,T12
0	1	4'b0011	-	-	Covered	T6,T7,T8
0	1	4'b1111	-	-	Covered	T6,T7,T9
0	1	default	-	-	Not Covered
0	0	-	1	4'b0010	Covered	T6,T7,T12
0	0	-	1	4'b0011	Covered	T6,T7,T8
0	0	-	1	4'b1111	Covered	T6,T7,T9
0	0	-	1	default	Not Covered
0	0	-	0	-	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	508	if ((!rst_ni))
-2-:	509	if ((((sram_req && mailbox_en_i) && cfg_intercept_en_mbx_i) && addr_d_in_mailbox))
-3-:	512	if ((((mailbox_en_i && cfg_intercept_en_mbx_i) && addr_d_in_mailbox) && (bitcnt == 3'b0)))
-4-:	516	if (((!addr_d_in_mailbox) && (bitcnt == 3'b0)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T1,T5
0	1	-	-	Covered	T6,T7,T23
0	0	1	-	Covered	T6,T7,T23
0	0	0	1	Covered	T4,T10,T6
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	529	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	547	if ((!sys_rst_ni))
-2-:	549	if (readbuf_flip)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T6,T7,T12
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	570	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	599	case (main_st)
-2-:	601	if ((sel_dp_i inside {DpReadCmd, DpReadSFDP}))
-3-:	613	if (addr_ready_in_word)
-4-:	617	if (addr_latched)
-5-:	626	case ({cmd_info_i.mbyte_en, cmd_info_i.dummy_en})
-6-:	654	if (s2p_valid_i)
-7-:	662	if (dummycnt_eq_zero)
-8-:	679	case (cmd_info_i.payload_en)
-9-:	686	if ((bitcnt == 3'b0))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
MainReset	1	-	-	-	-	-	-	-	Covered	T6,T7,T12
MainReset	0	-	-	-	-	-	-	-	Covered	T4,T1,T5
MainAddress	-	1	-	-	-	-	-	-	Covered	T6,T7,T12
MainAddress	-	0	-	-	-	-	-	-	Covered	T6,T7,T12
MainAddress	-	-	1	2'b00	-	-	-	-	Covered	T6,T7,T12
MainAddress	-	-	1	2'b01	-	-	-	-	Covered	T6,T7,T9
MainAddress	-	-	1	2'b1z	-	-	-	-	Not Covered
MainAddress	-	-	1	default	-	-	-	-	Not Covered
MainAddress	-	-	0	-	-	-	-	-	Covered	T6,T7,T12
MainMByte	-	-	-	-	1	-	-	-	Not Covered
MainMByte	-	-	-	-	0	-	-	-	Not Covered
MainDummy	-	-	-	-	-	1	-	-	Covered	T6,T7,T9
MainDummy	-	-	-	-	-	0	-	-	Covered	T6,T7,T9
MainOutput	-	-	-	-	-	-	4'b0010	-	Covered	T6,T7,T12
MainOutput	-	-	-	-	-	-	4'b0011	-	Covered	T6,T7,T8
MainOutput	-	-	-	-	-	-	4'b1111	-	Covered	T6,T7,T9
MainOutput	-	-	-	-	-	-	default	-	Not Covered
MainOutput	-	-	-	-	-	-	-	1	Covered	T6,T7,T12
MainOutput	-	-	-	-	-	-	-	0	Covered	T6,T7,T12
MainError	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spi_readcmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrIncNotAssertInAddressState_A	397838743	4793562	0	0
MailboxSizeMatch_M	397838743	349859748	0	0
ValidCmdConfig_A	397838743	221004	0	0

AddrIncNotAssertInAddressState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	4793562	0	0
T6	103085	31328	0	0
T7	131277	51437	0	0
T8	146466	5068	0	0
T9	13338	3437	0	0
T11	93697	0	0	0
T12	148629	6514	0	0
T13	122009	0	0	0
T14	0	52068	0	0
T15	0	4272	0	0
T23	114645	2573	0	0
T24	29758	0	0	0
T28	0	3404	0	0
T31	0	3949	0	0
T33	385	0	0	0

MailboxSizeMatch_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

ValidCmdConfig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	221004	0	0
T6	103085	1287	0	0
T7	131277	2212	0	0
T8	146466	200	0	0
T9	13338	200	0	0
T11	93697	0	0	0
T12	148629	124	0	0
T13	122009	0	0	0
T14	0	1642	0	0
T15	0	193	0	0
T23	114645	393	0	0
T24	29758	0	0	0
T28	0	208	0	0
T31	0	192	0	0
T33	385	0	0	0