Unified Coverage Report :: Module :: spi_cmdparse

Module : spi_cmdparse

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.06	100.00	97.33		100.00	97.96	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_cmdparse	99.06	100.00	97.33		100.00	97.96	100.00

---

Module Instance : tb.dut.u_cmdparse

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.06	100.00	97.33		100.00	97.96	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.06	100.00	97.33		100.00	97.96	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_cmdparse

	Line No.	Total	Covered	Percent
TOTAL		104	104	100.00
CONT_ASSIGN	74	1	1	100.00
ALWAYS	79	3	3	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	174	4	4	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	185	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	193	1	1	100.00
ALWAYS	197	4	4	100.00
ALWAYS	216	6	6	100.00
ALWAYS	230	7	7	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
ALWAYS	259	5	5	100.00
CONT_ASSIGN	274	1	1	100.00
ALWAYS	278	11	11	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	298	4	4	100.00
ALWAYS	306	45	45	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
74	1	1
79	1	1
80	1	1
81	1	1
145	1	1
149	1	1
174	1	1
175	1	1
176	1	1
178	1	1
			MISSING_ELSE
183	1	1
185	1	1
187	1	1
189	1	1
191	1	1
193	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
216	1	1
217	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE
230	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
			MISSING_ELSE
			MISSING_ELSE
249	1	1
250	1	1
259	1	1
264	1	1
266	1	1
267	1	1
268	1	1
			MISSING_ELSE
274	1	1
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	2	2
			MISSING_ELSE
284	2	2
			MISSING_ELSE
285	2	2
			MISSING_ELSE
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
298	1	1
299	1	1
300	1	1
301	1	1
			MISSING_ELSE
306	1	1
308	1	1
309	1	1
311	1	1
313	1	1
315	1	1
317	1	1
319	1	1
321	1	1
323	1	1
324	1	1
325	1	1
326	1	1
327	1	1
329	1	1
334	1	1
335	1	1
336	1	1
337	1	1
338	1	1
340	1	1
346	1	1
347	1	1
348	1	1
349	1	1
350	1	1
353	1	1
361	1	1
365	1	1
366	1	1
370	1	1
373	1	1
377	1	1
380	1	1
390	1	1
392	1	1
			MISSING_ELSE
397	1	1
399	1	1
401	1	1
403	1	1
405	1	1
407	1	1
409	1	1
412	1	1
414	1	1

---

Cond Coverage for Module : spi_cmdparse

	Total	Covered	Percent
Conditions	75	73	97.33
Logical	75	73	97.33
Non-Logical	0	0
Event	0	0

 LINE       176
 EXPRESSION (cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode))
             ---------------------1--------------------    ---------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T10,T6
1	1	Covered	T4,T10,T6

 LINE       176
 SUB-EXPRESSION (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)
                ---------------------------1---------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       183
 EXPRESSION (cmd_info_i[CmdInfoReadJedecId].valid && (data_i == cmd_info_i[CmdInfoReadJedecId].opcode))
             ------------------1-----------------    ------------------------2------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T10,T6
1	1	Covered	T4,T10,T6

 LINE       183
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadJedecId].opcode)
                ------------------------1------------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       185
 EXPRESSION (cmd_info_i[CmdInfoReadSfdp].valid && (data_i == cmd_info_i[CmdInfoReadSfdp].opcode))
             ----------------1----------------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T6,T7,T12
1	1	Covered	T6,T7,T12

 LINE       185
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadSfdp].opcode)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       187
 EXPRESSION (cmd_info_i[CmdInfoEn4B].valid && (data_i == cmd_info_i[CmdInfoEn4B].opcode))
             --------------1--------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       187
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEn4B].opcode)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       189
 EXPRESSION (cmd_info_i[CmdInfoEx4B].valid && (data_i == cmd_info_i[CmdInfoEx4B].opcode))
             --------------1--------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       189
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEx4B].opcode)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       191
 EXPRESSION (cmd_info_i[CmdInfoWrEn].valid && (data_i == cmd_info_i[CmdInfoWrEn].opcode))
             --------------1--------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       191
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrEn].opcode)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       193
 EXPRESSION (cmd_info_i[CmdInfoWrDi].valid && (data_i == cmd_info_i[CmdInfoWrDi].opcode))
             --------------1--------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

 LINE       193
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrDi].opcode)
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       199
 EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
             ---------1---------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T10,T6
1	1	Covered	T4,T10,T6

 LINE       199
 SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T2

 LINE       236
 EXPRESSION ((st == StIdle) && module_active && data_valid_i)
             -------1------    ------2------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T10,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T1,T5
1	1	1	Covered	T4,T10,T6

 LINE       236
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T4,T10,T6
1	Covered	T4,T1,T5

 LINE       238
 EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
             ---------1---------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T17
1	0	Covered	T4,T10,T6
1	1	Covered	T4,T10,T6

 LINE       238
 SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T4,T10,T6
1	Covered	T4,T10,T6

 LINE       266
 EXPRESSION ((st == StIdle) && module_active && data_valid_i)
             -------1------    ------2------    ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T10,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T1,T5
1	1	1	Covered	T4,T10,T6

 LINE       266
 SUB-EXPRESSION (st == StIdle)
                -------1------

-1-	Status	Tests
0	Covered	T4,T10,T6
1	Covered	T4,T1,T5

 LINE       293
 EXPRESSION (spi_mode_i == FlashMode)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       294
 EXPRESSION (spi_mode_i == PassThrough)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T10,T6

 LINE       295
 EXPRESSION (in_flashmode || in_passthrough)
             ------1-----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T6
1	0	Covered	T4,T1,T5

 LINE       317
 EXPRESSION (module_active && data_valid_i && cmd_info_d.valid)
             ------1------    ------2-----    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T4,T10,T6
1	1	1	Covered	T4,T10,T6

 LINE       373
 EXPRESSION (opcode_en4b ? DpEn4B : DpEx4B)
             -----1-----

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T6,T7,T23

 LINE       380
 EXPRESSION (opcode_wren ? DpWrEn : DpWrDi)
             -----1-----

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T6,T7,T8

 LINE       390
 EXPRESSION (module_active && data_valid_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T10,T6

---

FSM Coverage for Module : spi_cmdparse

Summary for FSM :: st

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAddr4B	370	Covered	T6,T7,T23
StIdle	236	Covered	T4,T1,T5
StJedec	335	Covered	T4,T6,T7
StReadCmd	361	Covered	T6,T7,T12
StSfdp	347	Covered	T6,T7,T23
StStatus	324	Covered	T6,T7,T8
StUpload	365	Covered	T6,T7,T8
StWait	329	Covered	T4,T10,T6
StWrEn	377	Covered	T6,T7,T8

transitions	Line No.	Covered	Tests
StIdle->StAddr4B	370	Covered	T6,T7,T23
StIdle->StJedec	335	Covered	T4,T6,T7
StIdle->StReadCmd	361	Covered	T6,T7,T12
StIdle->StSfdp	347	Covered	T6,T7,T23
StIdle->StStatus	324	Covered	T6,T7,T8
StIdle->StUpload	365	Covered	T6,T7,T8
StIdle->StWait	329	Covered	T4,T10,T6
StIdle->StWrEn	377	Covered	T6,T7,T8

---

Branch Coverage for Module : spi_cmdparse

	Line No.	Total	Covered	Percent
Branches		49	48	97.96
IF	176	2	2	100.00
IF	199	2	2	100.00
IF	216	3	3	100.00
IF	236	2	2	100.00
IF	266	2	2	100.00
IF	278	8	8	100.00
IF	298	3	3	100.00
CASE	315	27	26	96.30

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	176	if ((cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)))

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	199	if ((cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode)))

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	216	if ((!rst_ni))
-2-:	223	if (latch_cmdinfo)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T4,T10,T6
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	236	if ((((st == StIdle) && module_active) && data_valid_i))

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	266	if ((((st == StIdle) && module_active) && data_valid_i))

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	278	if ((!rst_ni))
-2-:	282	if (intercept_d)
-3-:	283	if (opcode_readstatus)
-4-:	284	if (opcode_readjedec)
-5-:	285	if (opcode_readsfdp)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T4,T1,T5
0	1	1	-	-	Covered	T6,T7,T8
0	1	0	-	-	Covered	T4,T6,T7
0	1	-	1	-	Covered	T4,T6,T7
0	1	-	0	-	Covered	T6,T7,T8
0	1	-	-	1	Covered	T6,T7,T14
0	1	-	-	0	Covered	T4,T6,T7
0	0	-	-	-	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	298	if ((!rst_ni))
-2-:	300	if (module_active)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T5
0	1	Covered	T4,T10,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	case (st)
-2-:	317	if (((module_active && data_valid_i) && cmd_info_d.valid))
-3-:	321	case (1'b1)
-4-:	323	if (in_flashmode)
-5-:	325	if (cfg_intercept_en_status_i)
-6-:	334	if (in_flashmode)
-7-:	336	if (cfg_intercept_en_jedec_i)
-8-:	346	if (in_flashmode)
-9-:	348	if (cfg_intercept_en_sfdp_i)
-10-:	373	(opcode_en4b) ? 
-11-:	380	(opcode_wren) ? 
-12-:	390	if ((module_active && data_valid_i))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	Status	Tests
StIdle	1	opcode_readstatus	1	-	-	-	-	-	-	-	-	Covered	T23,T29,T93
StIdle	1	opcode_readstatus	0	1	-	-	-	-	-	-	-	Covered	T6,T7,T8
StIdle	1	opcode_readstatus	0	0	-	-	-	-	-	-	-	Covered	T4,T10,T111
StIdle	1	opcode_readjedec	-	-	1	-	-	-	-	-	-	Covered	T23,T29,T93
StIdle	1	opcode_readjedec	-	-	0	1	-	-	-	-	-	Covered	T4,T6,T7
StIdle	1	opcode_readjedec	-	-	0	0	-	-	-	-	-	Covered	T10,T6,T7
StIdle	1	opcode_readsfdp	-	-	-	-	1	-	-	-	-	Covered	T23,T29,T30
StIdle	1	opcode_readsfdp	-	-	-	-	0	1	-	-	-	Covered	T6,T7,T14
StIdle	1	opcode_readsfdp	-	-	-	-	0	0	-	-	-	Covered	T6,T7,T12
StIdle	1	opcode_readcmd	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T12
StIdle	1	upload	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
StIdle	1	opcode_en4b opcode_ex4b	-	-	-	-	-	-	1	-	-	Covered	T6,T7,T23
StIdle	1	opcode_en4b opcode_ex4b	-	-	-	-	-	-	0	-	-	Covered	T6,T7,T23
StIdle	1	opcode_wren opcode_wrdi	-	-	-	-	-	-	-	1	-	Covered	T6,T7,T8
StIdle	1	opcode_wren opcode_wrdi	-	-	-	-	-	-	-	0	-	Covered	T6,T7,T8
StIdle	1	default	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T12
StIdle	0	-	-	-	-	-	-	-	-	-	1	Covered	T4,T10,T6
StIdle	0	-	-	-	-	-	-	-	-	-	0	Covered	T4,T1,T5
StStatus	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
StJedec	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
StSfdp	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T23
StReadCmd	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T12
StUpload	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
StAddr4B	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T23
StWrEn	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
StWait	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T10,T6
default	-	-	-	-	-	-	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spi_cmdparse

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CmdOnlySelDpKnown_A	397838743	349859748	0	0
OnlyOneDatapath_A	397838743	63333	0	0
SelDpKnown_A	397838743	349859748	0	0
StKnown_A	397838743	349859748	0	0

CmdOnlySelDpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

OnlyOneDatapath_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	63333	0	0
T1	49089	0	0	0
T2	385	0	0	0
T3	2913	0	0	0
T4	226674	22	0	0
T6	103085	719	0	0
T7	131277	608	0	0
T8	0	48	0	0
T9	0	8	0	0
T10	211932	24	0	0
T11	93697	0	0	0
T12	148629	16	0	0
T13	122009	0	0	0
T23	0	172	0	0
T24	0	22	0	0
T92	0	22	0	0

SelDpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0

StKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	397838743	349859748	0	0
T1	49089	49088	0	0
T2	385	384	0	0
T3	2913	2904	0	0
T4	226674	226320	0	0
T6	103085	102716	0	0
T7	131277	128055	0	0
T9	0	13338	0	0
T10	211932	211456	0	0
T11	93697	93696	0	0
T12	148629	148222	0	0
T13	122009	0	0	0