Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

154079824

1

T1

61735

T4

21

T2

640

full_word

18773994

1

T1

30406

T4

1082

T2

207

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	172853488	1			T1	92141		T4	1103		T2	847
auto[TlIntgErrCmd]	114	1			T71	6		T130	11		T134	7
auto[TlIntgErrData]	111	1			T71	6		T130	8		T134	6
auto[TlIntgErrBoth]	105	1			T71	8		T130	11		T134	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160859080

1

T1

74839

T4

20

T2

686

auto[1]

11994738

1

T1

17302

T4

1083

T2

161

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	153776400	1			T1	61733		T4	16		T2	638
auto[TlIntgErrNone]	partial	auto[1]	303124	1			T1	2		T4	5		T2	2
auto[TlIntgErrNone]	full_word	auto[0]	7082542	1			T1	13106		T4	4		T2	48
auto[TlIntgErrNone]	full_word	auto[1]	11691422	1			T1	17300		T4	1078		T2	159
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T71	1		T130	4		T134	4
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T71	4		T130	4		T134	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T163	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T71	1		T130	3		T162	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T71	2		T130	4		T134	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T71	3		T130	3		T134	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T71	1		T134	1		T162	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T130	1		T166	1		T163	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T71	5		T130	2		T134	4
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T71	1		T130	9		T134	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T71	1		T166	1		T192	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T71	1		T192	2		T163	1