Unified Coverage Report :: Module :: spid_jedec

Module : spid_jedec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	100.00		100.00	96.88	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_jedec	99.38	100.00	100.00		100.00	96.88	100.00

---

Module Instance : tb.dut.u_jedec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	100.00		100.00	96.88	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	100.00		100.00	96.88	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_jedec

	Line No.	Total	Covered	Percent
TOTAL		47	47	100.00
CONT_ASSIGN	64	1	1	100.00
ALWAYS	72	4	4	100.00
CONT_ASSIGN	78	1	1	100.00
ALWAYS	82	4	4	100.00
ALWAYS	90	5	5	100.00
ALWAYS	100	8	8	100.00
ALWAYS	120	4	4	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	131	3	3	100.00
ALWAYS	137	16	16	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
64	1	1
72	2	2
73	2	2
			MISSING_ELSE
78	1	1
82	2	2
83	1	1
84	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1
100	1	1
102	1	1
104	1	1
105	1	1
106	1	1
107	1	1
108	1	1
112	1	1
120	2	2
121	2	2
			MISSING_ELSE
124	1	1
131	2	2
132	1	1
137	1	1
139	1	1
140	1	1
142	1	1
144	1	1
145	1	1
148	1	1
			MISSING_ELSE
159	1	1
160	1	1
			MISSING_ELSE
163	1	1
167	1	1
168	1	1
			MISSING_ELSE
171	1	1
178	1	1
180	1	1
181	1	1
			MISSING_ELSE

---

Cond Coverage for Module : spid_jedec

	Total	Covered	Percent
Conditions	29	29	100.00
Logical	29	29	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION ((st_q == StCC) && outclk_p2s_sent_i)
             -------1------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6
1	1	Covered	T3,T5,T6

 LINE       83
 SUB-EXPRESSION (st_q == StCC)
                -------1------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T5,T6

 LINE       102
 EXPRESSION (st_q == StIdle)
            --------1-------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T4,T2

 LINE       104
 EXPRESSION (cc_needed ? jedec.cc : jedec.jedec_id)
             ----1----

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T4,T3,T9

 LINE       105
 EXPRESSION (st_q == StCC)
            -------1------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       107
 EXPRESSION (st_q == StJedecId)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       112
 EXPRESSION ((byte_sel_q >= 2'b10) ? 8'b0 : ((byte_sel_q == 2'b1) ? jedec.device_id[15:8] : jedec.device_id[7:0]))
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       112
 SUB-EXPRESSION ((byte_sel_q == 2'b1) ? jedec.device_id[15:8] : jedec.device_id[7:0])
                 ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       112
 SUB-EXPRESSION (byte_sel_q == 2'b1)
                ----------1---------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       124
 EXPRESSION ((byte_sel_q == 2'b10) ? 2'b10 : ((byte_sel_q + 1'b1)))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T5,T6

 LINE       124
 SUB-EXPRESSION (byte_sel_q == 2'b10)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T5,T6

 LINE       144
 EXPRESSION (sel_dp_i == DpReadJEDEC)
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T5,T6

 LINE       145
 EXPRESSION (cc_needed ? StCC : StJedecId)
             ----1----

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

 LINE       159
 EXPRESSION (cc_count == jedec.num_cc)
            -------------1------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T5,T6

---

FSM Coverage for Module : spid_jedec

Summary for FSM :: st_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StCC	145	Covered	T3,T5,T6
StDevId	168	Covered	T3,T5,T6
StIdle	102	Covered	T1,T4,T2
StJedecId	145	Covered	T3,T5,T6

transitions	Line No.	Covered	Tests
StCC->StJedecId	160	Covered	T3,T5,T6
StIdle->StCC	145	Covered	T3,T5,T6
StIdle->StJedecId	145	Covered	T3,T5,T6
StJedecId->StDevId	168	Covered	T3,T5,T6

---

Branch Coverage for Module : spid_jedec

	Line No.	Total	Covered	Percent
Branches		32	31	96.88
TERNARY	124	2	2	100.00
IF	72	3	3	100.00
IF	82	3	3	100.00
IF	90	2	2	100.00
IF	102	7	7	100.00
IF	120	3	3	100.00
IF	131	2	2	100.00
CASE	142	10	9	90.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_jedec.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	124	((byte_sel_q == 2'b10)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	72	if ((!rst_ni))
-2-:	73	if (inclk_csb_asserted_pulse_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T2
0	1	Covered	T1,T4,T2
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	82	if ((!rst_ni))
-2-:	83	if (((st_q == StCC) && outclk_p2s_sent_i))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T2
0	1	Covered	T3,T5,T6
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	102	if ((st_q == StIdle))
-2-:	104	(cc_needed) ? 
-3-:	105	if ((st_q == StCC))
-4-:	107	if ((st_q == StJedecId))
-5-:	112	((byte_sel_q >= 2'b10)) ? 
-6-:	112	((byte_sel_q == 2'b1)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	1	-	-	-	-	Covered	T4,T3,T9
1	0	-	-	-	-	Covered	T1,T4,T2
0	-	1	-	-	-	Covered	T3,T5,T6
0	-	0	1	-	-	Covered	T3,T5,T6
0	-	0	0	1	-	Covered	T3,T5,T6
0	-	0	0	0	1	Covered	T3,T5,T6
0	-	0	0	0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	120	if ((!rst_ni))
-2-:	121	if (next_byte)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T2
0	1	Covered	T3,T5,T6
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	131	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	142	case (st_q)
-2-:	144	if ((sel_dp_i == DpReadJEDEC))
-3-:	145	(cc_needed) ? 
-4-:	159	if ((cc_count == jedec.num_cc))
-5-:	167	if (outclk_p2s_sent_i)
-6-:	180	if (outclk_p2s_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle	1	1	-	-	-	Covered	T3,T5,T6
StIdle	1	0	-	-	-	Covered	T3,T5,T6
StIdle	0	-	-	-	-	Covered	T1,T4,T2
StCC	-	-	1	-	-	Covered	T3,T5,T6
StCC	-	-	0	-	-	Covered	T3,T5,T6
StJedecId	-	-	-	1	-	Covered	T3,T5,T6
StJedecId	-	-	-	0	-	Covered	T3,T5,T6
StDevId	-	-	-	-	1	Covered	T3,T5,T6
StDevId	-	-	-	-	0	Covered	T3,T5,T6
default	-	-	-	-	-	Not Covered

---

Assert Coverage for Module : spid_jedec

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
JedecStKnown_A	377358845	320917221	0	0

JedecStKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	320917221	0	0
T1	419394	419392	0	0
T2	1537	1536	0	0
T3	152345	104658	0	0
T4	10518	10368	0	0
T7	671220	333312	0	0
T8	0	68992	0	0
T9	101788	101288	0	0
T10	78745	77988	0	0
T11	33589	33328	0	0
T12	1537	1536	0	0
T13	62565	0	0	0