Unified Coverage Report :: Module Instance :: tb.dut.u_sys_sram_arbiter.u_req_fifo

Module Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.85	100.00	65.38			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.96	100.00	65.38			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00				100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
ALWAYS	70	4	4	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
ALWAYS	165	2	2	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	180	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
92	1	1
93	1	1
98	1	1
99	1	1
100	1	1
145	1	1
146	1	1
162	1	1
165	1	1
166	1	1
			MISSING_ELSE
175	1	1
176	1	1
180	1	1

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	26	17	65.38
Logical	26	17	65.38
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (3'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value)))))

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Not Covered

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((3'(gen_normal_fifo.wptr_value) - 3'(gen_normal_fifo.rptr_value))) : (((3'(Depth) - 3'(gen_normal_fifo.rptr_value)) + 3'(gen_normal_fifo.wptr_value))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T2

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T2

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Not Covered

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T4,T2

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T2

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	88	3	2	66.67
TERNARY	180	2	2	100.00
IF	70	3	3	100.00
IF	165	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	88	(gen_normal_fifo.full) ? 
-2-:	88	((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T4,T2
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	180	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	72	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T4,T2
0	1	Covered	T1,T4,T2
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	165	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1925754656	4807887	0	0
DepthKnown_A	1925754656	1925622518	0	0
RvalidKnown_A	1925754656	1925622518	0	0
WreadyKnown_A	1925754656	1925622518	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1925754656	4807887	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	4807887	0	0
T1	791675	13106	0	0
T2	10038	48	0	0
T3	600062	5029	0	0
T4	88106	0	0	0
T5	0	687	0	0
T7	489939	10416	0	0
T8	0	2156	0	0
T9	515659	0	0	0
T10	160576	0	0	0
T11	104891	0	0	0
T12	23539	48	0	0
T13	251228	0	0	0
T32	0	1865	0	0
T33	0	6	0	0
T34	0	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	1925622518	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T10	160576	160484	0	0
T12	23539	23479	0	0
T13	251228	251165	0	0
T42	1284	1197	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	1925622518	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T10	160576	160484	0	0
T12	23539	23479	0	0
T13	251228	251165	0	0
T42	1284	1197	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	1925622518	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T10	160576	160484	0	0
T12	23539	23479	0	0
T13	251228	251165	0	0
T42	1284	1197	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	4807887	0	0
T1	791675	13106	0	0
T2	10038	48	0	0
T3	600062	5029	0	0
T4	88106	0	0	0
T5	0	687	0	0
T7	489939	10416	0	0
T8	0	2156	0	0
T9	515659	0	0	0
T10	160576	0	0	0
T11	104891	0	0	0
T12	23539	48	0	0
T13	251228	0	0	0
T32	0	1865	0	0
T33	0	6	0	0
T34	0	50	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1928233267	228640725	0	0
DepthKnown_A	1928233267	1928061067	0	0
RvalidKnown_A	1928233267	1928061067	0	0
WreadyKnown_A	1928233267	1928061067	0	0
gen_passthru_fifo.paramCheckPass	1782	1782	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	228640725	0	0
T1	791675	209803	0	0
T2	10038	852	0	0
T3	600062	156615	0	0
T4	88106	1103	0	0
T7	489939	332950	0	0
T9	515659	2143	0	0
T13	251228	10820	0	0
T69	16499	2735	0	0
T70	11211	3166	0	0
T71	69910	21885	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1782	1782	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1928233267	281877453	0	0
DepthKnown_A	1928233267	1928061067	0	0
RvalidKnown_A	1928233267	1928061067	0	0
WreadyKnown_A	1928233267	1928061067	0	0
gen_passthru_fifo.paramCheckPass	1782	1782	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	281877453	0	0
T1	791675	449850	0	0
T2	10038	847	0	0
T3	600062	144080	0	0
T4	88106	1103	0	0
T7	489939	325390	0	0
T9	515659	1120	0	0
T13	251228	10805	0	0
T69	16499	2515	0	0
T70	11211	6190	0	0
T71	69910	41913	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1782	1782	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1928233267	13431384	0	0
DepthKnown_A	1928233267	1928061067	0	0
RvalidKnown_A	1928233267	1928061067	0	0
WreadyKnown_A	1928233267	1928061067	0	0
gen_passthru_fifo.paramCheckPass	1782	1782	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	13431384	0	0
T1	791675	51193	0	0
T2	10038	96	0	0
T3	600062	47402	0	0
T4	88106	1024	0	0
T7	489939	20874	0	0
T9	515659	2047	0	0
T13	251228	0	0	0
T70	11211	665	0	0
T72	3488	128	0	0
T73	16776	641	0	0
T74	0	5456	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1782	1782	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1928233267	23350448	0	0
DepthKnown_A	1928233267	1928061067	0	0
RvalidKnown_A	1928233267	1928061067	0	0
WreadyKnown_A	1928233267	1928061067	0	0
gen_passthru_fifo.paramCheckPass	1782	1782	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	23350448	0	0
T1	791675	128230	0	0
T2	10038	96	0	0
T3	600062	36139	0	0
T4	88106	1024	0	0
T7	489939	20832	0	0
T9	515659	1024	0	0
T13	251228	0	0	0
T70	11211	2016	0	0
T72	3488	250	0	0
T73	16776	627	0	0
T74	0	9234	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1782	1782	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1928233267	210762850	0	0
DepthKnown_A	1928233267	1928061067	0	0
RvalidKnown_A	1928233267	1928061067	0	0
WreadyKnown_A	1928233267	1928061067	0	0
gen_passthru_fifo.paramCheckPass	1782	1782	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	210762850	0	0
T1	791675	141223	0	0
T2	10038	756	0	0
T3	600062	108731	0	0
T4	88106	79	0	0
T7	489939	311309	0	0
T9	515659	96	0	0
T13	251228	10820	0	0
T69	16499	2735	0	0
T70	11211	1663	0	0
T71	69910	21885	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1782	1782	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1928233267	258527005	0	0
DepthKnown_A	1928233267	1928061067	0	0
RvalidKnown_A	1928233267	1928061067	0	0
WreadyKnown_A	1928233267	1928061067	0	0
gen_passthru_fifo.paramCheckPass	1782	1782	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	258527005	0	0
T1	791675	321620	0	0
T2	10038	751	0	0
T3	600062	107941	0	0
T4	88106	79	0	0
T7	489939	304558	0	0
T9	515659	96	0	0
T13	251228	10805	0	0
T69	16499	2515	0	0
T70	11211	4174	0	0
T71	69910	41913	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1928233267	1928061067	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T13	251228	251165	0	0
T69	16499	16324	0	0
T70	11211	11121	0	0
T71	69910	68130	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1782	1782	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0