Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_fwmode_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.53	100.00

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T4,T2

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T4,T2

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T4,T2
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	4821	4821	0	0
GntImpliesReady_A	2147483647	21425829	0	0
GntImpliesValid_A	2147483647	21425829	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	21425829	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	0	0	0
ReadyAndValidImplyGrant_A	2147483647	21425829	0	0
ReqAndReadyImplyGrant_A	2147483647	21425829	0	0
ReqImpliesValid_A	2147483647	21425829	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	835	0	2320
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	21425829	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2002645	2002563	0	0
T2	21482	21423	0	0
T3	1014642	924857	0	0
T4	109142	108782	0	0
T7	1651088	1313172	0	0
T8	0	68992	0	0
T9	719235	718179	0	0
T10	318066	316460	0	0
T11	33589	66656	0	0
T12	48537	48476	0	0
T13	376358	251165	0	0
T42	2470	2383	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4821	4821	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T7	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T12	3	3	0	0
T13	3	3	0	0
T42	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21425829	0	0
T1	1583251	52424	0	0
T2	19945	192	0	0
T3	1014642	47624	0	0
T4	98624	1024	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	1651088	41664	0	0
T8	0	4312	0	0
T9	719235	1024	0	0
T10	239321	3072	0	0
T11	0	1024	0	0
T12	47000	192	0	0
T13	376358	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T42	2470	6	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21425829	0	0
T1	1583251	52424	0	0
T2	19945	192	0	0
T3	1014642	47624	0	0
T4	98624	1024	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	1651088	41664	0	0
T8	0	4312	0	0
T9	719235	1024	0	0
T10	239321	3072	0	0
T11	0	1024	0	0
T12	47000	192	0	0
T13	376358	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T42	2470	6	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2002645	2002563	0	0
T2	21482	21423	0	0
T3	1014642	924857	0	0
T4	109142	108782	0	0
T7	1651088	1313172	0	0
T8	0	68992	0	0
T9	719235	718179	0	0
T10	318066	316460	0	0
T11	33589	66656	0	0
T12	48537	48476	0	0
T13	376358	251165	0	0
T42	2470	2383	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2002645	2002563	0	0
T2	21482	21423	0	0
T3	1014642	924857	0	0
T4	109142	108782	0	0
T7	1651088	1313172	0	0
T8	0	68992	0	0
T9	719235	718179	0	0
T10	318066	316460	0	0
T11	33589	66656	0	0
T12	48537	48476	0	0
T13	376358	251165	0	0
T42	2470	2383	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21425829	0	0
T1	1583251	52424	0	0
T2	19945	192	0	0
T3	1014642	47624	0	0
T4	98624	1024	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	1651088	41664	0	0
T8	0	4312	0	0
T9	719235	1024	0	0
T10	239321	3072	0	0
T11	0	1024	0	0
T12	47000	192	0	0
T13	376358	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T42	2470	6	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21425829	0	0
T1	1583251	52424	0	0
T2	19945	192	0	0
T3	1014642	47624	0	0
T4	98624	1024	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	1651088	41664	0	0
T8	0	4312	0	0
T9	719235	1024	0	0
T10	239321	3072	0	0
T11	0	1024	0	0
T12	47000	192	0	0
T13	376358	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T42	2470	6	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21425829	0	0
T1	1583251	52424	0	0
T2	19945	192	0	0
T3	1014642	47624	0	0
T4	98624	1024	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	1651088	41664	0	0
T8	0	4312	0	0
T9	719235	1024	0	0
T10	239321	3072	0	0
T11	0	1024	0	0
T12	47000	192	0	0
T13	376358	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T42	2470	6	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21425829	0	0
T1	1583251	52424	0	0
T2	19945	192	0	0
T3	1014642	47624	0	0
T4	98624	1024	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	1651088	41664	0	0
T8	0	4312	0	0
T9	719235	1024	0	0
T10	239321	3072	0	0
T11	0	1024	0	0
T12	47000	192	0	0
T13	376358	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T42	2470	6	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	835	0	2320
T44	121134	2	0	0
T47	599278	18	0	1
T48	739113	89	0	1
T49	0	1	0	1
T50	0	4	0	1
T51	0	5	0	0
T52	0	30	0	0
T53	0	3	0	0
T54	0	4	0	0
T55	0	5	0	0
T56	10319	0	0	0
T57	18826	0	0	1
T58	15363	0	0	1
T59	44927	0	0	0
T60	158865	0	0	1
T61	48138	0	0	0
T62	1468	0	0	1
T63	0	0	0	0
T64	0	0	0	0
T65	0	0	0	0
T66	0	0	0	1
T67	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2002645	2002563	0	0
T2	21482	21423	0	0
T3	1014642	924857	0	0
T4	109142	108782	0	0
T7	1651088	1313172	0	0
T8	0	68992	0	0
T9	719235	718179	0	0
T10	318066	316460	0	0
T11	33589	66656	0	0
T12	48537	48476	0	0
T13	376358	251165	0	0
T42	2470	2383	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21425829	0	0
T1	1583251	52424	0	0
T2	19945	192	0	0
T3	1014642	47624	0	0
T4	98624	1024	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	1651088	41664	0	0
T8	0	4312	0	0
T9	719235	1024	0	0
T10	239321	3072	0	0
T11	0	1024	0	0
T12	47000	192	0	0
T13	376358	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T42	2470	6	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T3,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T3,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	377358845	320917221	0	0
CheckNGreaterZero_A	1607	1607	0	0
GntImpliesReady_A	377358845	569110	0	0
GntImpliesValid_A	377358845	569110	0	0
GrantKnown_A	377358845	320917221	0	0
IdxKnown_A	377358845	320917221	0	0
IndexIsCorrect_A	377358845	569110	0	0
LockArbDecision_A	377358845	0	0	0
NoReadyValidNoGrant_A	377358845	0	0	0
ReadyAndValidImplyGrant_A	377358845	569110	0	0
ReqAndReadyImplyGrant_A	377358845	569110	0	0
ReqImpliesValid_A	377358845	569110	0	0
ReqStaysHighUntilGranted0_M	377358845	0	0	0
RoundRobin_A	377358845	0	0	0
ValidKnown_A	377358845	320917221	0	0
gen_data_port_assertion.DataFlow_A	377358845	569110	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	320917221	0	0
T1	419394	419392	0	0
T2	1537	1536	0	0
T3	152345	104658	0	0
T4	10518	10368	0	0
T7	671220	333312	0	0
T8	0	68992	0	0
T9	101788	101288	0	0
T10	78745	77988	0	0
T11	33589	33328	0	0
T12	1537	1536	0	0
T13	62565	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1607	1607	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T42	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	569110	0	0
T3	152345	2372	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	671220	0	0	0
T9	101788	0	0	0
T13	62565	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T20	0	5688	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0
T68	0	5223	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	569110	0	0
T3	152345	2372	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	671220	0	0	0
T9	101788	0	0	0
T13	62565	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T20	0	5688	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0
T68	0	5223	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	320917221	0	0
T1	419394	419392	0	0
T2	1537	1536	0	0
T3	152345	104658	0	0
T4	10518	10368	0	0
T7	671220	333312	0	0
T8	0	68992	0	0
T9	101788	101288	0	0
T10	78745	77988	0	0
T11	33589	33328	0	0
T12	1537	1536	0	0
T13	62565	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	320917221	0	0
T1	419394	419392	0	0
T2	1537	1536	0	0
T3	152345	104658	0	0
T4	10518	10368	0	0
T7	671220	333312	0	0
T8	0	68992	0	0
T9	101788	101288	0	0
T10	78745	77988	0	0
T11	33589	33328	0	0
T12	1537	1536	0	0
T13	62565	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	569110	0	0
T3	152345	2372	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	671220	0	0	0
T9	101788	0	0	0
T13	62565	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T20	0	5688	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0
T68	0	5223	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	569110	0	0
T3	152345	2372	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	671220	0	0	0
T9	101788	0	0	0
T13	62565	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T20	0	5688	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0
T68	0	5223	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	569110	0	0
T3	152345	2372	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	671220	0	0	0
T9	101788	0	0	0
T13	62565	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T20	0	5688	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0
T68	0	5223	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	569110	0	0
T3	152345	2372	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	671220	0	0	0
T9	101788	0	0	0
T13	62565	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T20	0	5688	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0
T68	0	5223	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	320917221	0	0
T1	419394	419392	0	0
T2	1537	1536	0	0
T3	152345	104658	0	0
T4	10518	10368	0	0
T7	671220	333312	0	0
T8	0	68992	0	0
T9	101788	101288	0	0
T10	78745	77988	0	0
T11	33589	33328	0	0
T12	1537	1536	0	0
T13	62565	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377358845	569110	0	0
T3	152345	2372	0	0
T5	850166	8976	0	0
T6	380120	2895	0	0
T7	671220	0	0	0
T9	101788	0	0	0
T13	62565	0	0	0
T15	0	8515	0	0
T17	0	8103	0	0
T18	45624	0	0	0
T20	0	5688	0	0
T36	526498	0	0	0
T37	21123	0	0	0
T43	0	4675	0	0
T44	0	2157	0	0
T45	0	1215	0	0
T46	97376	0	0	0
T68	0	5223	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T3,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T4,T2

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T4,T2

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T4,T2
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1925754656	1925622518	0	0
CheckNGreaterZero_A	1607	1607	0	0
GntImpliesReady_A	1925754656	11618158	0	0
GntImpliesValid_A	1925754656	11618158	0	0
GrantKnown_A	1925754656	1925622518	0	0
IdxKnown_A	1925754656	1925622518	0	0
IndexIsCorrect_A	1925754656	11618158	0	0
LockArbDecision_A	1925754656	0	0	0
NoReadyValidNoGrant_A	1925754656	0	0	0
ReadyAndValidImplyGrant_A	1925754656	11618158	0	0
ReqAndReadyImplyGrant_A	1925754656	11618158	0	0
ReqImpliesValid_A	1925754656	11618158	0	0
ReqStaysHighUntilGranted0_M	1925754656	0	0	0
RoundRobin_A	1925754656	0	0	1607
ValidKnown_A	1925754656	1925622518	0	0
gen_data_port_assertion.DataFlow_A	1925754656	11618158	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	1925622518	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T10	160576	160484	0	0
T12	23539	23479	0	0
T13	251228	251165	0	0
T42	1284	1197	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1607	1607	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T42	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	11618158	0	0
T1	791675	26212	0	0
T2	10038	96	0	0
T3	600062	36186	0	0
T4	88106	1024	0	0
T7	489939	20832	0	0
T9	515659	1024	0	0
T10	160576	3072	0	0
T11	0	1024	0	0
T12	23539	96	0	0
T13	251228	0	0	0
T42	1284	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	11618158	0	0
T1	791675	26212	0	0
T2	10038	96	0	0
T3	600062	36186	0	0
T4	88106	1024	0	0
T7	489939	20832	0	0
T9	515659	1024	0	0
T10	160576	3072	0	0
T11	0	1024	0	0
T12	23539	96	0	0
T13	251228	0	0	0
T42	1284	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	1925622518	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T10	160576	160484	0	0
T12	23539	23479	0	0
T13	251228	251165	0	0
T42	1284	1197	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	1925622518	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T10	160576	160484	0	0
T12	23539	23479	0	0
T13	251228	251165	0	0
T42	1284	1197	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	11618158	0	0
T1	791675	26212	0	0
T2	10038	96	0	0
T3	600062	36186	0	0
T4	88106	1024	0	0
T7	489939	20832	0	0
T9	515659	1024	0	0
T10	160576	3072	0	0
T11	0	1024	0	0
T12	23539	96	0	0
T13	251228	0	0	0
T42	1284	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	11618158	0	0
T1	791675	26212	0	0
T2	10038	96	0	0
T3	600062	36186	0	0
T4	88106	1024	0	0
T7	489939	20832	0	0
T9	515659	1024	0	0
T10	160576	3072	0	0
T11	0	1024	0	0
T12	23539	96	0	0
T13	251228	0	0	0
T42	1284	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	11618158	0	0
T1	791675	26212	0	0
T2	10038	96	0	0
T3	600062	36186	0	0
T4	88106	1024	0	0
T7	489939	20832	0	0
T9	515659	1024	0	0
T10	160576	3072	0	0
T11	0	1024	0	0
T12	23539	96	0	0
T13	251228	0	0	0
T42	1284	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	11618158	0	0
T1	791675	26212	0	0
T2	10038	96	0	0
T3	600062	36186	0	0
T4	88106	1024	0	0
T7	489939	20832	0	0
T9	515659	1024	0	0
T10	160576	3072	0	0
T11	0	1024	0	0
T12	23539	96	0	0
T13	251228	0	0	0
T42	1284	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	0	0	1607

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	1925622518	0	0
T1	791675	791595	0	0
T2	10038	9980	0	0
T3	600062	600047	0	0
T4	88106	88046	0	0
T7	489939	489931	0	0
T9	515659	515603	0	0
T10	160576	160484	0	0
T12	23539	23479	0	0
T13	251228	251165	0	0
T42	1284	1197	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925754656	11618158	0	0
T1	791675	26212	0	0
T2	10038	96	0	0
T3	600062	36186	0	0
T4	88106	1024	0	0
T7	489939	20832	0	0
T9	515659	1024	0	0
T10	160576	3072	0	0
T11	0	1024	0	0
T12	23539	96	0	0
T13	251228	0	0	0
T42	1284	4	0	0

Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1577831001	1539705934	0	0
CheckNGreaterZero_A	1607	1607	0	0
GntImpliesReady_A	1577831001	9238561	0	0
GntImpliesValid_A	1577831001	9238561	0	0
GrantKnown_A	1577831001	1539705934	0	0
IdxKnown_A	1577831001	1539705934	0	0
IndexIsCorrect_A	1577831001	9238561	0	0
LockArbDecision_A	1577831001	0	0	0
NoReadyValidNoGrant_A	1577831001	0	0	0
ReadyAndValidImplyGrant_A	1577831001	9238561	0	0
ReqAndReadyImplyGrant_A	1577831001	9238561	0	0
ReqImpliesValid_A	1577831001	9238561	0	0
ReqStaysHighUntilGranted0_M	1577831001	0	0	0
RoundRobin_A	1577831001	835	0	713
ValidKnown_A	1577831001	1539705934	0	0
gen_data_port_assertion.DataFlow_A	1577831001	9238561	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	1539705934	0	0
T1	791576	791576	0	0
T2	9907	9907	0	0
T3	262235	220152	0	0
T4	10518	10368	0	0
T7	489929	489929	0	0
T9	101788	101288	0	0
T10	78745	77988	0	0
T11	0	33328	0	0
T12	23461	23461	0	0
T13	62565	0	0	0
T42	1186	1186	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1607	1607	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T42	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	9238561	0	0
T1	791576	26212	0	0
T2	9907	96	0	0
T3	262235	9066	0	0
T4	10518	0	0	0
T7	489929	20832	0	0
T8	0	4312	0	0
T9	101788	0	0	0
T10	78745	0	0	0
T12	23461	96	0	0
T13	62565	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T42	1186	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	9238561	0	0
T1	791576	26212	0	0
T2	9907	96	0	0
T3	262235	9066	0	0
T4	10518	0	0	0
T7	489929	20832	0	0
T8	0	4312	0	0
T9	101788	0	0	0
T10	78745	0	0	0
T12	23461	96	0	0
T13	62565	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T42	1186	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	1539705934	0	0
T1	791576	791576	0	0
T2	9907	9907	0	0
T3	262235	220152	0	0
T4	10518	10368	0	0
T7	489929	489929	0	0
T9	101788	101288	0	0
T10	78745	77988	0	0
T11	0	33328	0	0
T12	23461	23461	0	0
T13	62565	0	0	0
T42	1186	1186	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	1539705934	0	0
T1	791576	791576	0	0
T2	9907	9907	0	0
T3	262235	220152	0	0
T4	10518	10368	0	0
T7	489929	489929	0	0
T9	101788	101288	0	0
T10	78745	77988	0	0
T11	0	33328	0	0
T12	23461	23461	0	0
T13	62565	0	0	0
T42	1186	1186	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	9238561	0	0
T1	791576	26212	0	0
T2	9907	96	0	0
T3	262235	9066	0	0
T4	10518	0	0	0
T7	489929	20832	0	0
T8	0	4312	0	0
T9	101788	0	0	0
T10	78745	0	0	0
T12	23461	96	0	0
T13	62565	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T42	1186	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	9238561	0	0
T1	791576	26212	0	0
T2	9907	96	0	0
T3	262235	9066	0	0
T4	10518	0	0	0
T7	489929	20832	0	0
T8	0	4312	0	0
T9	101788	0	0	0
T10	78745	0	0	0
T12	23461	96	0	0
T13	62565	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T42	1186	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	9238561	0	0
T1	791576	26212	0	0
T2	9907	96	0	0
T3	262235	9066	0	0
T4	10518	0	0	0
T7	489929	20832	0	0
T8	0	4312	0	0
T9	101788	0	0	0
T10	78745	0	0	0
T12	23461	96	0	0
T13	62565	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T42	1186	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	9238561	0	0
T1	791576	26212	0	0
T2	9907	96	0	0
T3	262235	9066	0	0
T4	10518	0	0	0
T7	489929	20832	0	0
T8	0	4312	0	0
T9	101788	0	0	0
T10	78745	0	0	0
T12	23461	96	0	0
T13	62565	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T42	1186	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	835	0	713
T44	121134	2	0	0
T47	599278	18	0	1
T48	739113	89	0	1
T49	0	1	0	1
T50	0	4	0	1
T51	0	5	0	0
T52	0	30	0	0
T53	0	3	0	0
T54	0	4	0	0
T55	0	5	0	0
T56	10319	0	0	0
T57	18826	0	0	1
T58	15363	0	0	1
T59	44927	0	0	0
T60	158865	0	0	1
T61	48138	0	0	0
T62	1468	0	0	1
T63	0	0	0	0
T64	0	0	0	0
T65	0	0	0	0
T66	0	0	0	1
T67	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	1539705934	0	0
T1	791576	791576	0	0
T2	9907	9907	0	0
T3	262235	220152	0	0
T4	10518	10368	0	0
T7	489929	489929	0	0
T9	101788	101288	0	0
T10	78745	77988	0	0
T11	0	33328	0	0
T12	23461	23461	0	0
T13	62565	0	0	0
T42	1186	1186	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1577831001	9238561	0	0
T1	791576	26212	0	0
T2	9907	96	0	0
T3	262235	9066	0	0
T4	10518	0	0	0
T7	489929	20832	0	0
T8	0	4312	0	0
T9	101788	0	0	0
T10	78745	0	0	0
T12	23461	96	0	0
T13	62565	0	0	0
T32	0	3730	0	0
T33	0	12	0	0
T34	0	100	0	0
T42	1186	2	0	0