Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
8176 |
0 |
0 |
T70 |
11211 |
299 |
0 |
0 |
T71 |
69910 |
4 |
0 |
0 |
T72 |
3488 |
2 |
0 |
0 |
T73 |
16776 |
661 |
0 |
0 |
T130 |
30081 |
2 |
0 |
0 |
T134 |
70745 |
6 |
0 |
0 |
T135 |
25757 |
692 |
0 |
0 |
T136 |
0 |
356 |
0 |
0 |
T159 |
2242 |
2 |
0 |
0 |
T160 |
1957 |
0 |
0 |
0 |
T161 |
4299 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2265 |
0 |
0 |
T71 |
69910 |
83 |
0 |
0 |
T72 |
3488 |
20 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
66 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
75 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
4 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
2 |
0 |
0 |
T192 |
0 |
30 |
0 |
0 |
T193 |
0 |
18 |
0 |
0 |
T194 |
0 |
16 |
0 |
0 |
T195 |
0 |
64 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2400 |
0 |
0 |
T71 |
69910 |
67 |
0 |
0 |
T72 |
3488 |
15 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
78 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
53 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
31 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
12 |
0 |
0 |
T192 |
0 |
41 |
0 |
0 |
T193 |
0 |
14 |
0 |
0 |
T194 |
0 |
16 |
0 |
0 |
T195 |
0 |
56 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
8386 |
0 |
0 |
T71 |
69910 |
1079 |
0 |
0 |
T72 |
3488 |
14 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
1731 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
1011 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
23 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
153 |
0 |
0 |
T192 |
0 |
820 |
0 |
0 |
T193 |
0 |
13 |
0 |
0 |
T194 |
0 |
36 |
0 |
0 |
T195 |
0 |
50 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
8705 |
0 |
0 |
T71 |
69910 |
1524 |
0 |
0 |
T72 |
3488 |
7 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
1263 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
1174 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
13 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
57 |
0 |
0 |
T192 |
0 |
849 |
0 |
0 |
T193 |
0 |
3 |
0 |
0 |
T194 |
0 |
19 |
0 |
0 |
T195 |
0 |
21 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
8079 |
0 |
0 |
T71 |
69910 |
1372 |
0 |
0 |
T72 |
3488 |
8 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
735 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
1382 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
31 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
141 |
0 |
0 |
T192 |
0 |
760 |
0 |
0 |
T193 |
0 |
2 |
0 |
0 |
T194 |
0 |
2 |
0 |
0 |
T195 |
0 |
33 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
6685 |
0 |
0 |
T71 |
69910 |
1121 |
0 |
0 |
T72 |
3488 |
21 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
1225 |
0 |
0 |
T135 |
0 |
3 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
702 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
14 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
158 |
0 |
0 |
T192 |
0 |
258 |
0 |
0 |
T193 |
0 |
15 |
0 |
0 |
T194 |
0 |
35 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
8423 |
0 |
0 |
T71 |
69910 |
1232 |
0 |
0 |
T72 |
3488 |
23 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
1257 |
0 |
0 |
T135 |
0 |
3 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
1220 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
8 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
146 |
0 |
0 |
T192 |
0 |
799 |
0 |
0 |
T193 |
0 |
10 |
0 |
0 |
T194 |
0 |
40 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
7840 |
0 |
0 |
T71 |
69910 |
1112 |
0 |
0 |
T72 |
3488 |
16 |
0 |
0 |
T134 |
70745 |
1540 |
0 |
0 |
T135 |
25757 |
0 |
0 |
0 |
T136 |
12307 |
0 |
0 |
0 |
T142 |
7792 |
0 |
0 |
0 |
T160 |
1957 |
0 |
0 |
0 |
T161 |
4299 |
0 |
0 |
0 |
T162 |
0 |
868 |
0 |
0 |
T165 |
65483 |
0 |
0 |
0 |
T168 |
16668 |
0 |
0 |
0 |
T176 |
0 |
139 |
0 |
0 |
T192 |
0 |
559 |
0 |
0 |
T193 |
0 |
7 |
0 |
0 |
T194 |
0 |
3 |
0 |
0 |
T195 |
0 |
89 |
0 |
0 |
T196 |
0 |
25 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
8125 |
0 |
0 |
T71 |
69910 |
1709 |
0 |
0 |
T72 |
3488 |
9 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
1311 |
0 |
0 |
T135 |
0 |
1 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
888 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
11 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
75 |
0 |
0 |
T192 |
0 |
645 |
0 |
0 |
T193 |
0 |
2 |
0 |
0 |
T194 |
0 |
25 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
8338 |
0 |
0 |
T71 |
69910 |
1301 |
0 |
0 |
T72 |
3488 |
14 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
1687 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
987 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
10 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
17 |
0 |
0 |
T192 |
0 |
521 |
0 |
0 |
T193 |
0 |
11 |
0 |
0 |
T194 |
0 |
34 |
0 |
0 |
T195 |
0 |
52 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4461 |
0 |
0 |
T71 |
69910 |
545 |
0 |
0 |
T72 |
3488 |
7 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
619 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
337 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
16 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
33 |
0 |
0 |
T192 |
0 |
206 |
0 |
0 |
T193 |
0 |
10 |
0 |
0 |
T194 |
0 |
30 |
0 |
0 |
T195 |
0 |
78 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4295 |
0 |
0 |
T71 |
69910 |
551 |
0 |
0 |
T72 |
3488 |
18 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
449 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
388 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
9 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
6 |
0 |
0 |
T192 |
0 |
265 |
0 |
0 |
T193 |
0 |
16 |
0 |
0 |
T194 |
0 |
14 |
0 |
0 |
T195 |
0 |
15 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
3956 |
0 |
0 |
T71 |
69910 |
567 |
0 |
0 |
T72 |
3488 |
10 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
319 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
362 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
10 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
11 |
0 |
0 |
T192 |
0 |
172 |
0 |
0 |
T193 |
0 |
2 |
0 |
0 |
T194 |
0 |
17 |
0 |
0 |
T195 |
0 |
46 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4036 |
0 |
0 |
T71 |
69910 |
533 |
0 |
0 |
T72 |
3488 |
5 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
548 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
347 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
3 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
43 |
0 |
0 |
T192 |
0 |
295 |
0 |
0 |
T193 |
0 |
17 |
0 |
0 |
T194 |
0 |
21 |
0 |
0 |
T195 |
0 |
20 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4070 |
0 |
0 |
T71 |
69910 |
369 |
0 |
0 |
T72 |
3488 |
7 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
358 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
343 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
17 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
31 |
0 |
0 |
T192 |
0 |
287 |
0 |
0 |
T193 |
0 |
10 |
0 |
0 |
T194 |
0 |
1 |
0 |
0 |
T195 |
0 |
56 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4470 |
0 |
0 |
T71 |
69910 |
326 |
0 |
0 |
T72 |
3488 |
13 |
0 |
0 |
T134 |
70745 |
563 |
0 |
0 |
T135 |
25757 |
0 |
0 |
0 |
T136 |
12307 |
0 |
0 |
0 |
T142 |
7792 |
0 |
0 |
0 |
T160 |
1957 |
0 |
0 |
0 |
T161 |
4299 |
0 |
0 |
0 |
T162 |
0 |
381 |
0 |
0 |
T165 |
65483 |
0 |
0 |
0 |
T168 |
16668 |
0 |
0 |
0 |
T176 |
0 |
31 |
0 |
0 |
T192 |
0 |
298 |
0 |
0 |
T193 |
0 |
8 |
0 |
0 |
T194 |
0 |
26 |
0 |
0 |
T195 |
0 |
34 |
0 |
0 |
T196 |
0 |
27 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4361 |
0 |
0 |
T71 |
69910 |
514 |
0 |
0 |
T72 |
3488 |
11 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
522 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
350 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
1 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
38 |
0 |
0 |
T192 |
0 |
236 |
0 |
0 |
T193 |
0 |
1 |
0 |
0 |
T194 |
0 |
46 |
0 |
0 |
T195 |
0 |
64 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4636 |
0 |
0 |
T71 |
69910 |
510 |
0 |
0 |
T72 |
3488 |
22 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
619 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
414 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
18 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
40 |
0 |
0 |
T192 |
0 |
266 |
0 |
0 |
T193 |
0 |
13 |
0 |
0 |
T194 |
0 |
29 |
0 |
0 |
T195 |
0 |
37 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4200 |
0 |
0 |
T71 |
69910 |
625 |
0 |
0 |
T72 |
3488 |
8 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
525 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
384 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
9 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
65 |
0 |
0 |
T192 |
0 |
232 |
0 |
0 |
T193 |
0 |
10 |
0 |
0 |
T194 |
0 |
18 |
0 |
0 |
T195 |
0 |
53 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
3953 |
0 |
0 |
T71 |
69910 |
459 |
0 |
0 |
T72 |
3488 |
11 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
252 |
0 |
0 |
T135 |
0 |
3 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
405 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
22 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
53 |
0 |
0 |
T192 |
0 |
214 |
0 |
0 |
T193 |
0 |
10 |
0 |
0 |
T194 |
0 |
24 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4321 |
0 |
0 |
T71 |
69910 |
430 |
0 |
0 |
T72 |
3488 |
9 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
429 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
518 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
4 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
6 |
0 |
0 |
T192 |
0 |
217 |
0 |
0 |
T193 |
0 |
6 |
0 |
0 |
T194 |
0 |
37 |
0 |
0 |
T195 |
0 |
52 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4469 |
0 |
0 |
T71 |
69910 |
665 |
0 |
0 |
T72 |
3488 |
17 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
650 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
441 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
3 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
20 |
0 |
0 |
T192 |
0 |
280 |
0 |
0 |
T193 |
0 |
9 |
0 |
0 |
T194 |
0 |
2 |
0 |
0 |
T195 |
0 |
23 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4359 |
0 |
0 |
T71 |
69910 |
522 |
0 |
0 |
T72 |
3488 |
16 |
0 |
0 |
T134 |
70745 |
356 |
0 |
0 |
T135 |
25757 |
0 |
0 |
0 |
T136 |
12307 |
0 |
0 |
0 |
T142 |
7792 |
0 |
0 |
0 |
T160 |
1957 |
0 |
0 |
0 |
T161 |
4299 |
0 |
0 |
0 |
T162 |
0 |
390 |
0 |
0 |
T165 |
65483 |
0 |
0 |
0 |
T168 |
16668 |
0 |
0 |
0 |
T176 |
0 |
52 |
0 |
0 |
T192 |
0 |
219 |
0 |
0 |
T193 |
0 |
9 |
0 |
0 |
T194 |
0 |
37 |
0 |
0 |
T195 |
0 |
78 |
0 |
0 |
T196 |
0 |
27 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4297 |
0 |
0 |
T71 |
69910 |
393 |
0 |
0 |
T72 |
3488 |
9 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
459 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
299 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
13 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
68 |
0 |
0 |
T192 |
0 |
222 |
0 |
0 |
T193 |
0 |
13 |
0 |
0 |
T194 |
0 |
4 |
0 |
0 |
T195 |
0 |
56 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4364 |
0 |
0 |
T71 |
69910 |
499 |
0 |
0 |
T72 |
3488 |
5 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
524 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
357 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
1 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
32 |
0 |
0 |
T192 |
0 |
268 |
0 |
0 |
T193 |
0 |
15 |
0 |
0 |
T194 |
0 |
22 |
0 |
0 |
T195 |
0 |
49 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4045 |
0 |
0 |
T71 |
69910 |
346 |
0 |
0 |
T72 |
3488 |
8 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
541 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
271 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
20 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
15 |
0 |
0 |
T192 |
0 |
177 |
0 |
0 |
T193 |
0 |
9 |
0 |
0 |
T194 |
0 |
12 |
0 |
0 |
T195 |
0 |
24 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4397 |
0 |
0 |
T71 |
69910 |
488 |
0 |
0 |
T72 |
3488 |
14 |
0 |
0 |
T134 |
70745 |
349 |
0 |
0 |
T135 |
25757 |
0 |
0 |
0 |
T136 |
12307 |
0 |
0 |
0 |
T142 |
7792 |
0 |
0 |
0 |
T160 |
1957 |
0 |
0 |
0 |
T161 |
4299 |
0 |
0 |
0 |
T162 |
0 |
373 |
0 |
0 |
T165 |
65483 |
0 |
0 |
0 |
T168 |
16668 |
0 |
0 |
0 |
T176 |
0 |
34 |
0 |
0 |
T192 |
0 |
315 |
0 |
0 |
T193 |
0 |
21 |
0 |
0 |
T194 |
0 |
24 |
0 |
0 |
T195 |
0 |
27 |
0 |
0 |
T196 |
0 |
35 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4146 |
0 |
0 |
T71 |
69910 |
534 |
0 |
0 |
T72 |
3488 |
9 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
316 |
0 |
0 |
T142 |
0 |
4 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
379 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
19 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
29 |
0 |
0 |
T192 |
0 |
392 |
0 |
0 |
T193 |
0 |
10 |
0 |
0 |
T194 |
0 |
12 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4529 |
0 |
0 |
T71 |
69910 |
453 |
0 |
0 |
T72 |
3488 |
10 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
497 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
495 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
12 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
9 |
0 |
0 |
T192 |
0 |
306 |
0 |
0 |
T193 |
0 |
7 |
0 |
0 |
T194 |
0 |
24 |
0 |
0 |
T195 |
0 |
10 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4327 |
0 |
0 |
T71 |
69910 |
366 |
0 |
0 |
T72 |
3488 |
1 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
635 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
414 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
9 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
31 |
0 |
0 |
T192 |
0 |
267 |
0 |
0 |
T193 |
0 |
1 |
0 |
0 |
T194 |
0 |
19 |
0 |
0 |
T195 |
0 |
75 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4181 |
0 |
0 |
T71 |
69910 |
365 |
0 |
0 |
T72 |
3488 |
6 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
556 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
424 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
5 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
30 |
0 |
0 |
T192 |
0 |
211 |
0 |
0 |
T193 |
0 |
12 |
0 |
0 |
T194 |
0 |
32 |
0 |
0 |
T195 |
0 |
9 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4200 |
0 |
0 |
T71 |
69910 |
564 |
0 |
0 |
T72 |
3488 |
21 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
602 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
365 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
8 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
16 |
0 |
0 |
T192 |
0 |
144 |
0 |
0 |
T193 |
0 |
4 |
0 |
0 |
T194 |
0 |
18 |
0 |
0 |
T195 |
0 |
52 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4549 |
0 |
0 |
T70 |
11211 |
9 |
0 |
0 |
T71 |
69910 |
496 |
0 |
0 |
T72 |
3488 |
6 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
685 |
0 |
0 |
T162 |
0 |
423 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
14 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
43 |
0 |
0 |
T192 |
0 |
237 |
0 |
0 |
T193 |
0 |
9 |
0 |
0 |
T194 |
0 |
41 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4249 |
0 |
0 |
T71 |
69910 |
602 |
0 |
0 |
T72 |
3488 |
17 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
612 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
299 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
6 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
13 |
0 |
0 |
T192 |
0 |
244 |
0 |
0 |
T193 |
0 |
5 |
0 |
0 |
T194 |
0 |
29 |
0 |
0 |
T195 |
0 |
87 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2698 |
0 |
0 |
T71 |
69910 |
124 |
0 |
0 |
T72 |
3488 |
23 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
152 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
124 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
1 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
30 |
0 |
0 |
T192 |
0 |
51 |
0 |
0 |
T193 |
0 |
5 |
0 |
0 |
T194 |
0 |
40 |
0 |
0 |
T195 |
0 |
45 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2535 |
0 |
0 |
T71 |
69910 |
97 |
0 |
0 |
T72 |
3488 |
7 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
142 |
0 |
0 |
T135 |
0 |
9 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
100 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
17 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
15 |
0 |
0 |
T192 |
0 |
64 |
0 |
0 |
T193 |
0 |
15 |
0 |
0 |
T194 |
0 |
15 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2670 |
0 |
0 |
T71 |
69910 |
86 |
0 |
0 |
T72 |
3488 |
19 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
115 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
99 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
11 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
12 |
0 |
0 |
T192 |
0 |
53 |
0 |
0 |
T193 |
0 |
14 |
0 |
0 |
T194 |
0 |
18 |
0 |
0 |
T195 |
0 |
40 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2676 |
0 |
0 |
T71 |
69910 |
107 |
0 |
0 |
T72 |
3488 |
14 |
0 |
0 |
T134 |
70745 |
156 |
0 |
0 |
T135 |
25757 |
0 |
0 |
0 |
T136 |
12307 |
0 |
0 |
0 |
T142 |
7792 |
0 |
0 |
0 |
T160 |
1957 |
0 |
0 |
0 |
T161 |
4299 |
0 |
0 |
0 |
T162 |
0 |
103 |
0 |
0 |
T165 |
65483 |
0 |
0 |
0 |
T168 |
16668 |
0 |
0 |
0 |
T176 |
0 |
33 |
0 |
0 |
T192 |
0 |
60 |
0 |
0 |
T193 |
0 |
4 |
0 |
0 |
T194 |
0 |
32 |
0 |
0 |
T195 |
0 |
47 |
0 |
0 |
T196 |
0 |
3 |
0 |
0 |
control_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
3317 |
0 |
0 |
T71 |
69910 |
259 |
0 |
0 |
T72 |
3488 |
16 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
299 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
245 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
1 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
14 |
0 |
0 |
T192 |
0 |
145 |
0 |
0 |
T193 |
0 |
10 |
0 |
0 |
T194 |
0 |
5 |
0 |
0 |
T195 |
0 |
59 |
0 |
0 |
fifo_level_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2474 |
0 |
0 |
T71 |
69910 |
121 |
0 |
0 |
T72 |
3488 |
12 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
121 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
66 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
30 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
6 |
0 |
0 |
T192 |
0 |
70 |
0 |
0 |
T193 |
0 |
10 |
0 |
0 |
T194 |
0 |
9 |
0 |
0 |
T195 |
0 |
11 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2876 |
0 |
0 |
T71 |
69910 |
186 |
0 |
0 |
T72 |
3488 |
10 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
168 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
164 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
7 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
4 |
0 |
0 |
T192 |
0 |
100 |
0 |
0 |
T193 |
0 |
7 |
0 |
0 |
T194 |
0 |
12 |
0 |
0 |
T195 |
0 |
26 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
4658 |
0 |
0 |
T71 |
69910 |
495 |
0 |
0 |
T72 |
3488 |
2 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T97 |
1799 |
27 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
584 |
0 |
0 |
T162 |
0 |
364 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
5 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
13 |
0 |
0 |
T176 |
0 |
9 |
0 |
0 |
T192 |
0 |
354 |
0 |
0 |
T197 |
0 |
6 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2298 |
0 |
0 |
T71 |
69910 |
86 |
0 |
0 |
T72 |
3488 |
24 |
0 |
0 |
T134 |
70745 |
102 |
0 |
0 |
T135 |
25757 |
0 |
0 |
0 |
T136 |
12307 |
6 |
0 |
0 |
T142 |
7792 |
0 |
0 |
0 |
T160 |
1957 |
0 |
0 |
0 |
T161 |
4299 |
0 |
0 |
0 |
T162 |
0 |
92 |
0 |
0 |
T165 |
65483 |
0 |
0 |
0 |
T168 |
16668 |
0 |
0 |
0 |
T176 |
0 |
13 |
0 |
0 |
T192 |
0 |
56 |
0 |
0 |
T193 |
0 |
14 |
0 |
0 |
T194 |
0 |
20 |
0 |
0 |
T195 |
0 |
20 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2523 |
0 |
0 |
T71 |
69910 |
111 |
0 |
0 |
T72 |
3488 |
18 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
106 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
75 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
8 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
22 |
0 |
0 |
T192 |
0 |
49 |
0 |
0 |
T193 |
0 |
12 |
0 |
0 |
T194 |
0 |
36 |
0 |
0 |
T195 |
0 |
16 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2468 |
0 |
0 |
T71 |
69910 |
77 |
0 |
0 |
T72 |
3488 |
11 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
90 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
83 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
14 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T192 |
0 |
43 |
0 |
0 |
T193 |
0 |
14 |
0 |
0 |
T194 |
0 |
17 |
0 |
0 |
T195 |
0 |
51 |
0 |
0 |
T196 |
0 |
24 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2371 |
0 |
0 |
T71 |
69910 |
62 |
0 |
0 |
T72 |
3488 |
8 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
71 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
32 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
28 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T192 |
0 |
29 |
0 |
0 |
T193 |
0 |
18 |
0 |
0 |
T194 |
0 |
24 |
0 |
0 |
T195 |
0 |
42 |
0 |
0 |
T196 |
0 |
31 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2386 |
0 |
0 |
T71 |
69910 |
94 |
0 |
0 |
T72 |
3488 |
18 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
72 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
86 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
35 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
12 |
0 |
0 |
T192 |
0 |
37 |
0 |
0 |
T193 |
0 |
12 |
0 |
0 |
T194 |
0 |
11 |
0 |
0 |
T195 |
0 |
37 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2335 |
0 |
0 |
T71 |
69910 |
79 |
0 |
0 |
T72 |
3488 |
5 |
0 |
0 |
T134 |
70745 |
77 |
0 |
0 |
T135 |
25757 |
5 |
0 |
0 |
T136 |
12307 |
0 |
0 |
0 |
T142 |
7792 |
0 |
0 |
0 |
T160 |
1957 |
0 |
0 |
0 |
T161 |
4299 |
0 |
0 |
0 |
T162 |
0 |
55 |
0 |
0 |
T165 |
65483 |
0 |
0 |
0 |
T168 |
16668 |
0 |
0 |
0 |
T176 |
0 |
4 |
0 |
0 |
T192 |
0 |
36 |
0 |
0 |
T193 |
0 |
15 |
0 |
0 |
T194 |
0 |
10 |
0 |
0 |
T195 |
0 |
28 |
0 |
0 |
rxf_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2682 |
0 |
0 |
T70 |
11211 |
7 |
0 |
0 |
T71 |
69910 |
89 |
0 |
0 |
T72 |
3488 |
18 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
118 |
0 |
0 |
T135 |
0 |
7 |
0 |
0 |
T142 |
0 |
1 |
0 |
0 |
T162 |
0 |
104 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
1 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
10 |
0 |
0 |
T192 |
0 |
52 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2966 |
0 |
0 |
T71 |
69910 |
176 |
0 |
0 |
T72 |
3488 |
13 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
259 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
102 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
33 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
19 |
0 |
0 |
T192 |
0 |
114 |
0 |
0 |
T193 |
0 |
11 |
0 |
0 |
T194 |
0 |
48 |
0 |
0 |
T195 |
0 |
26 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2438 |
0 |
0 |
T71 |
69910 |
76 |
0 |
0 |
T72 |
3488 |
7 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
84 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
51 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
1 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
12 |
0 |
0 |
T192 |
0 |
40 |
0 |
0 |
T193 |
0 |
7 |
0 |
0 |
T194 |
0 |
4 |
0 |
0 |
T195 |
0 |
30 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
3147 |
0 |
0 |
T71 |
69910 |
302 |
0 |
0 |
T72 |
3488 |
7 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
146 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
175 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
17 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
15 |
0 |
0 |
T192 |
0 |
136 |
0 |
0 |
T193 |
0 |
17 |
0 |
0 |
T194 |
0 |
17 |
0 |
0 |
T195 |
0 |
59 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2530 |
0 |
0 |
T70 |
11211 |
3 |
0 |
0 |
T71 |
69910 |
123 |
0 |
0 |
T72 |
3488 |
12 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
100 |
0 |
0 |
T162 |
0 |
72 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
14 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
10 |
0 |
0 |
T192 |
0 |
40 |
0 |
0 |
T193 |
0 |
6 |
0 |
0 |
T194 |
0 |
27 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2284 |
0 |
0 |
T70 |
11211 |
7 |
0 |
0 |
T71 |
69910 |
88 |
0 |
0 |
T72 |
3488 |
17 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
67 |
0 |
0 |
T135 |
0 |
6 |
0 |
0 |
T162 |
0 |
39 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
37 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
8 |
0 |
0 |
T192 |
0 |
25 |
0 |
0 |
T193 |
0 |
19 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2317 |
0 |
0 |
T71 |
69910 |
87 |
0 |
0 |
T72 |
3488 |
10 |
0 |
0 |
T134 |
70745 |
90 |
0 |
0 |
T135 |
25757 |
0 |
0 |
0 |
T136 |
12307 |
0 |
0 |
0 |
T142 |
7792 |
0 |
0 |
0 |
T160 |
1957 |
0 |
0 |
0 |
T161 |
4299 |
0 |
0 |
0 |
T162 |
0 |
60 |
0 |
0 |
T165 |
65483 |
0 |
0 |
0 |
T168 |
16668 |
0 |
0 |
0 |
T176 |
0 |
13 |
0 |
0 |
T192 |
0 |
42 |
0 |
0 |
T193 |
0 |
7 |
0 |
0 |
T194 |
0 |
1 |
0 |
0 |
T195 |
0 |
29 |
0 |
0 |
T196 |
0 |
16 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2424 |
0 |
0 |
T71 |
69910 |
97 |
0 |
0 |
T72 |
3488 |
5 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
76 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
79 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
15 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
8 |
0 |
0 |
T192 |
0 |
39 |
0 |
0 |
T193 |
0 |
18 |
0 |
0 |
T194 |
0 |
16 |
0 |
0 |
T195 |
0 |
44 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2415 |
0 |
0 |
T71 |
69910 |
84 |
0 |
0 |
T72 |
3488 |
10 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
63 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
47 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
21 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
7 |
0 |
0 |
T192 |
0 |
37 |
0 |
0 |
T193 |
0 |
9 |
0 |
0 |
T194 |
0 |
10 |
0 |
0 |
T195 |
0 |
54 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2433 |
0 |
0 |
T71 |
69910 |
60 |
0 |
0 |
T72 |
3488 |
17 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
75 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
76 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
32 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
10 |
0 |
0 |
T192 |
0 |
46 |
0 |
0 |
T193 |
0 |
16 |
0 |
0 |
T194 |
0 |
21 |
0 |
0 |
T195 |
0 |
35 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2248 |
0 |
0 |
T71 |
69910 |
87 |
0 |
0 |
T72 |
3488 |
4 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
97 |
0 |
0 |
T135 |
0 |
9 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
20 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
10 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
14 |
0 |
0 |
T192 |
0 |
22 |
0 |
0 |
T193 |
0 |
7 |
0 |
0 |
T194 |
0 |
25 |
0 |
0 |
txf_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1928233267 |
2457 |
0 |
0 |
T71 |
69910 |
83 |
0 |
0 |
T72 |
3488 |
7 |
0 |
0 |
T74 |
21502 |
0 |
0 |
0 |
T98 |
1535 |
0 |
0 |
0 |
T99 |
1071 |
0 |
0 |
0 |
T134 |
0 |
116 |
0 |
0 |
T158 |
1499 |
0 |
0 |
0 |
T162 |
0 |
90 |
0 |
0 |
T170 |
132949 |
0 |
0 |
0 |
T171 |
7159 |
6 |
0 |
0 |
T172 |
775 |
0 |
0 |
0 |
T173 |
1283 |
0 |
0 |
0 |
T176 |
0 |
4 |
0 |
0 |
T192 |
0 |
26 |
0 |
0 |
T193 |
0 |
10 |
0 |
0 |
T194 |
0 |
37 |
0 |
0 |
T195 |
0 |
30 |
0 |
0 |