Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_cmdparse
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.06 100.00 97.33 100.00 97.96 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_cmdparse 99.06 100.00 97.33 100.00 97.96 100.00



Module Instance : tb.dut.u_cmdparse

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.06 100.00 97.33 100.00 97.96 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.06 100.00 97.33 100.00 97.96 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.39 96.31 94.03 97.00 93.33 96.30 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spi_cmdparse
Line No.TotalCoveredPercent
TOTAL104104100.00
CONT_ASSIGN7411100.00
ALWAYS7933100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14911100.00
ALWAYS17444100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19111100.00
CONT_ASSIGN19311100.00
ALWAYS19744100.00
ALWAYS21666100.00
ALWAYS23077100.00
CONT_ASSIGN24911100.00
CONT_ASSIGN25011100.00
ALWAYS25955100.00
CONT_ASSIGN27411100.00
ALWAYS2781111100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29511100.00
ALWAYS29844100.00
ALWAYS3064545100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
74 1 1
79 1 1
80 1 1
81 1 1
145 1 1
149 1 1
174 1 1
175 1 1
176 1 1
178 1 1
MISSING_ELSE
183 1 1
185 1 1
187 1 1
189 1 1
191 1 1
193 1 1
197 1 1
198 1 1
199 1 1
200 1 1
MISSING_ELSE
216 1 1
217 1 1
222 1 1
223 1 1
224 1 1
225 1 1
MISSING_ELSE
230 1 1
235 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
MISSING_ELSE
MISSING_ELSE
249 1 1
250 1 1
259 1 1
264 1 1
266 1 1
267 1 1
268 1 1
MISSING_ELSE
274 1 1
278 1 1
279 1 1
280 1 1
281 1 1
282 1 1
283 2 2
MISSING_ELSE
284 2 2
MISSING_ELSE
285 2 2
MISSING_ELSE
MISSING_ELSE
293 1 1
294 1 1
295 1 1
298 1 1
299 1 1
300 1 1
301 1 1
MISSING_ELSE
306 1 1
308 1 1
309 1 1
311 1 1
313 1 1
315 1 1
317 1 1
319 1 1
321 1 1
323 1 1
324 1 1
325 1 1
326 1 1
327 1 1
329 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
340 1 1
346 1 1
347 1 1
348 1 1
349 1 1
350 1 1
353 1 1
361 1 1
365 1 1
366 1 1
370 1 1
373 1 1
377 1 1
380 1 1
390 1 1
392 1 1
MISSING_ELSE
397 1 1
399 1 1
401 1 1
403 1 1
405 1 1
407 1 1
409 1 1
412 1 1
414 1 1


Cond Coverage for Module : spi_cmdparse
TotalCoveredPercent
Conditions757397.33
Logical757397.33
Non-Logical00
Event00

 LINE       176
 EXPRESSION (cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode))
             ---------------------1--------------------    ---------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT4,T3,T10
11CoveredT4,T3,T10

 LINE       176
 SUB-EXPRESSION (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)
                ---------------------------1---------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       183
 EXPRESSION (cmd_info_i[CmdInfoReadJedecId].valid && (data_i == cmd_info_i[CmdInfoReadJedecId].opcode))
             ------------------1-----------------    ------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT3,T10,T19
11CoveredT3,T10,T5

 LINE       183
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadJedecId].opcode)
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       185
 EXPRESSION (cmd_info_i[CmdInfoReadSfdp].valid && (data_i == cmd_info_i[CmdInfoReadSfdp].opcode))
             ----------------1----------------    -----------------------2----------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T3,T9
11CoveredT4,T3,T9

 LINE       185
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoReadSfdp].opcode)
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       187
 EXPRESSION (cmd_info_i[CmdInfoEn4B].valid && (data_i == cmd_info_i[CmdInfoEn4B].opcode))
             --------------1--------------    ---------------------2--------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T3,T19
11CoveredT4,T3,T19

 LINE       187
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEn4B].opcode)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       189
 EXPRESSION (cmd_info_i[CmdInfoEx4B].valid && (data_i == cmd_info_i[CmdInfoEx4B].opcode))
             --------------1--------------    ---------------------2--------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T3,T19
11CoveredT4,T3,T19

 LINE       189
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoEx4B].opcode)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       191
 EXPRESSION (cmd_info_i[CmdInfoWrEn].valid && (data_i == cmd_info_i[CmdInfoWrEn].opcode))
             --------------1--------------    ---------------------2--------------------
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT3,T19,T5
11CoveredT3,T5,T6

 LINE       191
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrEn].opcode)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       193
 EXPRESSION (cmd_info_i[CmdInfoWrDi].valid && (data_i == cmd_info_i[CmdInfoWrDi].opcode))
             --------------1--------------    ---------------------2--------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T3,T19
11CoveredT4,T3,T19

 LINE       193
 SUB-EXPRESSION (data_i == cmd_info_i[CmdInfoWrDi].opcode)
                ---------------------1--------------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       199
 EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
             ---------1---------    ----------------2---------------
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT4,T3,T9
11CoveredT4,T3,T9

 LINE       199
 SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       236
 EXPRESSION ((st == StIdle) && module_active && data_valid_i)
             -------1------    ------2------    ------3-----
-1--2--3-StatusTests
011CoveredT4,T3,T9
101CoveredT1,T2,T3
110CoveredT1,T4,T2
111CoveredT4,T3,T9

 LINE       236
 SUB-EXPRESSION (st == StIdle)
                -------1------
-1-StatusTests
0CoveredT4,T3,T9
1CoveredT1,T4,T2

 LINE       238
 EXPRESSION (cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode))
             ---------1---------    ----------------2---------------
-1--2-StatusTests
01CoveredT9,T10,T11
10CoveredT4,T3,T9
11CoveredT4,T3,T9

 LINE       238
 SUB-EXPRESSION (data_i == cmd_info_i[i].opcode)
                ----------------1---------------
-1-StatusTests
0CoveredT4,T3,T9
1CoveredT4,T3,T9

 LINE       266
 EXPRESSION ((st == StIdle) && module_active && data_valid_i)
             -------1------    ------2------    ------3-----
-1--2--3-StatusTests
011CoveredT4,T3,T9
101CoveredT1,T2,T3
110CoveredT1,T4,T2
111CoveredT4,T3,T9

 LINE       266
 SUB-EXPRESSION (st == StIdle)
                -------1------
-1-StatusTests
0CoveredT4,T3,T9
1CoveredT1,T4,T2

 LINE       293
 EXPRESSION (spi_mode_i == FlashMode)
            ------------1------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT1,T4,T2

 LINE       294
 EXPRESSION (spi_mode_i == PassThrough)
            -------------1-------------
-1-StatusTests
0CoveredT1,T4,T2
1CoveredT4,T9,T11

 LINE       295
 EXPRESSION (in_flashmode || in_passthrough)
             ------1-----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T9,T11
10CoveredT1,T4,T2

 LINE       317
 EXPRESSION (module_active && data_valid_i && cmd_info_d.valid)
             ------1------    ------2-----    --------3-------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT4,T3,T9
111CoveredT4,T3,T9

 LINE       373
 EXPRESSION (opcode_en4b ? DpEn4B : DpEx4B)
             -----1-----
-1-StatusTests
0CoveredT4,T3,T19
1CoveredT3,T19,T5

 LINE       380
 EXPRESSION (opcode_wren ? DpWrEn : DpWrDi)
             -----1-----
-1-StatusTests
0CoveredT4,T3,T19
1CoveredT3,T5,T6

 LINE       390
 EXPRESSION (module_active && data_valid_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T2
11CoveredT4,T3,T9

FSM Coverage for Module : spi_cmdparse
Summary for FSM :: st
TotalCoveredPercent
States 9 9 100.00 (Not included in score)
Transitions 8 8 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st
statesLine No.CoveredTests
StAddr4B 370 Covered T4,T3,T19
StIdle 236 Covered T1,T4,T2
StJedec 335 Covered T3,T5,T6
StReadCmd 361 Covered T3,T9,T10
StSfdp 347 Covered T3,T11,T5
StStatus 324 Covered T3,T5,T6
StUpload 365 Covered T3,T5,T6
StWait 329 Covered T4,T3,T9
StWrEn 377 Covered T4,T3,T19


transitionsLine No.CoveredTests
StIdle->StAddr4B 370 Covered T4,T3,T19
StIdle->StJedec 335 Covered T3,T5,T6
StIdle->StReadCmd 361 Covered T3,T9,T10
StIdle->StSfdp 347 Covered T3,T11,T5
StIdle->StStatus 324 Covered T3,T5,T6
StIdle->StUpload 365 Covered T3,T5,T6
StIdle->StWait 329 Covered T4,T3,T9
StIdle->StWrEn 377 Covered T4,T3,T19



Branch Coverage for Module : spi_cmdparse
Line No.TotalCoveredPercent
Branches 49 48 97.96
IF 176 2 2 100.00
IF 199 2 2 100.00
IF 216 3 3 100.00
IF 236 2 2 100.00
IF 266 2 2 100.00
IF 278 8 8 100.00
IF 298 3 3 100.00
CASE 315 27 26 96.30

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_cmdparse.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 176 if ((cmd_info_i[(CmdInfoReadStatus1 + i)].valid && (data_i == cmd_info_i[(CmdInfoReadStatus1 + i)].opcode)))

Branches:
-1-StatusTests
1 Covered T4,T3,T10
0 Covered T1,T4,T2


LineNo. Expression -1-: 199 if ((cmd_info_i[i].valid && (data_i == cmd_info_i[i].opcode)))

Branches:
-1-StatusTests
1 Covered T4,T3,T9
0 Covered T1,T4,T2


LineNo. Expression -1-: 216 if ((!rst_ni)) -2-: 223 if (latch_cmdinfo)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T4,T3,T9
0 0 Covered T1,T4,T2


LineNo. Expression -1-: 236 if ((((st == StIdle) && module_active) && data_valid_i))

Branches:
-1-StatusTests
1 Covered T4,T3,T9
0 Covered T1,T4,T2


LineNo. Expression -1-: 266 if ((((st == StIdle) && module_active) && data_valid_i))

Branches:
-1-StatusTests
1 Covered T4,T3,T9
0 Covered T1,T4,T2


LineNo. Expression -1-: 278 if ((!rst_ni)) -2-: 282 if (intercept_d) -3-: 283 if (opcode_readstatus) -4-: 284 if (opcode_readjedec) -5-: 285 if (opcode_readsfdp)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T4,T2
0 1 1 - - Covered T18,T15,T17
0 1 0 - - Covered T11,T18,T15
0 1 - 1 - Covered T18,T15,T17
0 1 - 0 - Covered T11,T18,T15
0 1 - - 1 Covered T11,T15,T16
0 1 - - 0 Covered T18,T15,T17
0 0 - - - Covered T1,T4,T2


LineNo. Expression -1-: 298 if ((!rst_ni)) -2-: 300 if (module_active)

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T2
0 1 Covered T4,T3,T9
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 315 case (st) -2-: 317 if (((module_active && data_valid_i) && cmd_info_d.valid)) -3-: 321 case (1'b1) -4-: 323 if (in_flashmode) -5-: 325 if (cfg_intercept_en_status_i) -6-: 334 if (in_flashmode) -7-: 336 if (cfg_intercept_en_jedec_i) -8-: 346 if (in_flashmode) -9-: 348 if (cfg_intercept_en_sfdp_i) -10-: 373 (opcode_en4b) ? -11-: 380 (opcode_wren) ? -12-: 390 if ((module_active && data_valid_i))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12-StatusTests
StIdle 1 opcode_readstatus 1 - - - - - - - - Covered T3,T5,T6
StIdle 1 opcode_readstatus 0 1 - - - - - - - Covered T18,T15,T17
StIdle 1 opcode_readstatus 0 0 - - - - - - - Covered T131,T132,T133
StIdle 1 opcode_readjedec - - 1 - - - - - - Covered T3,T5,T6
StIdle 1 opcode_readjedec - - 0 1 - - - - - Covered T18,T15,T17
StIdle 1 opcode_readjedec - - 0 0 - - - - - Covered T15,T17,T131
StIdle 1 opcode_readsfdp - - - - 1 - - - - Covered T3,T5,T6
StIdle 1 opcode_readsfdp - - - - 0 1 - - - Covered T11,T15,T16
StIdle 1 opcode_readsfdp - - - - 0 0 - - - Covered T18,T15,T17
StIdle 1 opcode_readcmd - - - - - - - - - Covered T3,T9,T10
StIdle 1 upload - - - - - - - - - Covered T3,T5,T6
StIdle 1 opcode_en4b opcode_ex4b - - - - - - 1 - - Covered T3,T19,T5
StIdle 1 opcode_en4b opcode_ex4b - - - - - - 0 - - Covered T4,T3,T19
StIdle 1 opcode_wren opcode_wrdi - - - - - - - 1 - Covered T3,T5,T6
StIdle 1 opcode_wren opcode_wrdi - - - - - - - 0 - Covered T4,T3,T19
StIdle 1 default - - - - - - - - - Covered T3,T14,T5
StIdle 0 - - - - - - - - - 1 Covered T4,T3,T9
StIdle 0 - - - - - - - - - 0 Covered T1,T4,T2
StStatus - - - - - - - - - - - Covered T3,T5,T6
StJedec - - - - - - - - - - - Covered T3,T5,T6
StSfdp - - - - - - - - - - - Covered T3,T11,T5
StReadCmd - - - - - - - - - - - Covered T3,T9,T10
StUpload - - - - - - - - - - - Covered T3,T5,T6
StAddr4B - - - - - - - - - - - Covered T4,T3,T19
StWrEn - - - - - - - - - - - Covered T4,T3,T19
StWait - - - - - - - - - - - Covered T4,T3,T9
default - - - - - - - - - - - Not Covered


Assert Coverage for Module : spi_cmdparse
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CmdOnlySelDpKnown_A 377358845 320917221 0 0
OnlyOneDatapath_A 377358845 65536 0 0
SelDpKnown_A 377358845 320917221 0 0
StKnown_A 377358845 320917221 0 0


CmdOnlySelDpKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 377358845 320917221 0 0
T1 419394 419392 0 0
T2 1537 1536 0 0
T3 152345 104658 0 0
T4 10518 10368 0 0
T7 671220 333312 0 0
T8 0 68992 0 0
T9 101788 101288 0 0
T10 78745 77988 0 0
T11 33589 33328 0 0
T12 1537 1536 0 0
T13 62565 0 0 0

OnlyOneDatapath_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 377358845 65536 0 0
T2 1537 0 0 0
T3 152345 751 0 0
T4 10518 10 0 0
T5 0 401 0 0
T6 0 555 0 0
T7 671220 0 0 0
T8 68994 0 0 0
T9 101788 24 0 0
T10 78745 26 0 0
T11 33589 20 0 0
T13 62565 0 0 0
T14 0 38 0 0
T18 0 38 0 0
T19 622 24 0 0

SelDpKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 377358845 320917221 0 0
T1 419394 419392 0 0
T2 1537 1536 0 0
T3 152345 104658 0 0
T4 10518 10368 0 0
T7 671220 333312 0 0
T8 0 68992 0 0
T9 101788 101288 0 0
T10 78745 77988 0 0
T11 33589 33328 0 0
T12 1537 1536 0 0
T13 62565 0 0 0

StKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 377358845 320917221 0 0
T1 419394 419392 0 0
T2 1537 1536 0 0
T3 152345 104658 0 0
T4 10518 10368 0 0
T7 671220 333312 0 0
T8 0 68992 0 0
T9 101788 101288 0 0
T10 78745 77988 0 0
T11 33589 33328 0 0
T12 1537 1536 0 0
T13 62565 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%