Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_fwmode_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.53	100.00

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T8
1	0	Covered	T2,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
1	0	Covered	T5,T1,T2

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Covered	T5,T1,T2

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Unreachable
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T4,T5,T1

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	4839	4839	0	0
GntImpliesReady_A	2147483647	21520425	0	0
GntImpliesValid_A	2147483647	21520425	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	21520425	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	0	0	0
ReadyAndValidImplyGrant_A	2147483647	21520425	0	0
ReqAndReadyImplyGrant_A	2147483647	21520425	0	0
ReqImpliesValid_A	2147483647	21520425	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	820	0	2331
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	21520425	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1929	1829	0	0
T2	80396	80328	0	0
T3	473701	440536	0	0
T4	2005	1905	0	0
T5	109036	108949	0	0
T6	1389996	1326192	0	0
T8	2667	2580	0	0
T9	2410	10850	0	0
T10	538023	447456	0	0
T11	483887	481249	0	0
T12	96770	96000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	10975	2719	0	0
T34	792	792	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4839	4839	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T8	3	3	0	0
T11	3	3	0	0
T15	3	3	0	0
T35	3	3	0	0
T36	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21520425	0	0
T1	1928	6	0	0
T2	77099	536	0	0
T3	473701	24413	0	0
T5	38636	1024	0	0
T6	1752544	21254	0	0
T7	688652	398	0	0
T8	2667	6	0	0
T9	8452	268	0	0
T10	0	27966	0	0
T11	483887	2048	0	0
T12	96770	1024	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	10975	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T33	0	43136	0	0
T34	792	5	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	1880	0	0
T45	0	29210	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21520425	0	0
T1	1928	6	0	0
T2	77099	536	0	0
T3	473701	24413	0	0
T5	38636	1024	0	0
T6	1752544	21254	0	0
T7	688652	398	0	0
T8	2667	6	0	0
T9	8452	268	0	0
T10	0	27966	0	0
T11	483887	2048	0	0
T12	96770	1024	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	10975	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T33	0	43136	0	0
T34	792	5	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	1880	0	0
T45	0	29210	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1929	1829	0	0
T2	80396	80328	0	0
T3	473701	440536	0	0
T4	2005	1905	0	0
T5	109036	108949	0	0
T6	1389996	1326192	0	0
T8	2667	2580	0	0
T9	2410	10850	0	0
T10	538023	447456	0	0
T11	483887	481249	0	0
T12	96770	96000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	10975	2719	0	0
T34	792	792	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1929	1829	0	0
T2	80396	80328	0	0
T3	473701	440536	0	0
T4	2005	1905	0	0
T5	109036	108949	0	0
T6	1389996	1326192	0	0
T8	2667	2580	0	0
T9	2410	10850	0	0
T10	538023	447456	0	0
T11	483887	481249	0	0
T12	96770	96000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	10975	2719	0	0
T34	792	792	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21520425	0	0
T1	1928	6	0	0
T2	77099	536	0	0
T3	473701	24413	0	0
T5	38636	1024	0	0
T6	1752544	21254	0	0
T7	688652	398	0	0
T8	2667	6	0	0
T9	8452	268	0	0
T10	0	27966	0	0
T11	483887	2048	0	0
T12	96770	1024	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	10975	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T33	0	43136	0	0
T34	792	5	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	1880	0	0
T45	0	29210	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21520425	0	0
T1	1928	6	0	0
T2	77099	536	0	0
T3	473701	24413	0	0
T5	38636	1024	0	0
T6	1752544	21254	0	0
T7	688652	398	0	0
T8	2667	6	0	0
T9	8452	268	0	0
T10	0	27966	0	0
T11	483887	2048	0	0
T12	96770	1024	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	10975	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T33	0	43136	0	0
T34	792	5	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	1880	0	0
T45	0	29210	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21520425	0	0
T1	1928	6	0	0
T2	77099	536	0	0
T3	473701	24413	0	0
T5	38636	1024	0	0
T6	1752544	21254	0	0
T7	688652	398	0	0
T8	2667	6	0	0
T9	8452	268	0	0
T10	0	27966	0	0
T11	483887	2048	0	0
T12	96770	1024	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	10975	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T33	0	43136	0	0
T34	792	5	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	1880	0	0
T45	0	29210	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21520425	0	0
T1	1928	6	0	0
T2	77099	536	0	0
T3	473701	24413	0	0
T5	38636	1024	0	0
T6	1752544	21254	0	0
T7	688652	398	0	0
T8	2667	6	0	0
T9	8452	268	0	0
T10	0	27966	0	0
T11	483887	2048	0	0
T12	96770	1024	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	10975	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T33	0	43136	0	0
T34	792	5	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	1880	0	0
T45	0	29210	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	820	0	2331
T7	289527	0	0	1
T17	73410	0	0	0
T23	0	0	0	0
T37	25826	0	0	0
T38	735204	0	0	0
T40	393588	1	0	1
T41	8208	0	0	0
T46	0	0	0	0
T47	16712	0	0	1
T48	328662	0	0	1
T49	696	0	0	0
T50	0	1	0	1
T51	0	1	0	1
T52	0	68	0	0
T53	0	3	0	0
T54	0	6	0	0
T55	0	1	0	0
T56	0	4	0	0
T57	0	6	0	0
T58	0	11	0	0
T59	112403	0	0	1
T60	0	0	0	0
T61	0	0	0	1
T62	0	0	0	1
T63	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1929	1829	0	0
T2	80396	80328	0	0
T3	473701	440536	0	0
T4	2005	1905	0	0
T5	109036	108949	0	0
T6	1389996	1326192	0	0
T8	2667	2580	0	0
T9	2410	10850	0	0
T10	538023	447456	0	0
T11	483887	481249	0	0
T12	96770	96000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	10975	2719	0	0
T34	792	792	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21520425	0	0
T1	1928	6	0	0
T2	77099	536	0	0
T3	473701	24413	0	0
T5	38636	1024	0	0
T6	1752544	21254	0	0
T7	688652	398	0	0
T8	2667	6	0	0
T9	8452	268	0	0
T10	0	27966	0	0
T11	483887	2048	0	0
T12	96770	1024	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	10975	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T33	0	43136	0	0
T34	792	5	0	0
T35	1138	0	0	0
T36	1666	0	0	0
T38	0	1880	0	0
T45	0	29210	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
1	0	Covered	T3,T6,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T2,T3
1	0	Unreachable
1	1	Covered	T3,T6,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T6,T7
0	0	1	Unreachable
0	0	0	Covered	T5,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410997401	359562642	0	0
CheckNGreaterZero_A	1613	1613	0	0
GntImpliesReady_A	410997401	547783	0	0
GntImpliesValid_A	410997401	547783	0	0
GrantKnown_A	410997401	359562642	0	0
IdxKnown_A	410997401	359562642	0	0
IndexIsCorrect_A	410997401	547783	0	0
LockArbDecision_A	410997401	0	0	0
NoReadyValidNoGrant_A	410997401	0	0	0
ReadyAndValidImplyGrant_A	410997401	547783	0	0
ReqAndReadyImplyGrant_A	410997401	547783	0	0
ReqImpliesValid_A	410997401	547783	0	0
ReqStaysHighUntilGranted0_M	410997401	0	0	0
RoundRobin_A	410997401	0	0	0
ValidKnown_A	410997401	359562642	0	0
gen_data_port_assertion.DataFlow_A	410997401	547783	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1613	1613	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	547783	0	0
T3	175606	4771	0	0
T6	694998	1486	0	0
T7	688652	398	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T23	0	9251	0	0
T26	0	9068	0	0
T38	0	1880	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	547783	0	0
T3	175606	4771	0	0
T6	694998	1486	0	0
T7	688652	398	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T23	0	9251	0	0
T26	0	9068	0	0
T38	0	1880	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	547783	0	0
T3	175606	4771	0	0
T6	694998	1486	0	0
T7	688652	398	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T23	0	9251	0	0
T26	0	9068	0	0
T38	0	1880	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	547783	0	0
T3	175606	4771	0	0
T6	694998	1486	0	0
T7	688652	398	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T23	0	9251	0	0
T26	0	9068	0	0
T38	0	1880	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	547783	0	0
T3	175606	4771	0	0
T6	694998	1486	0	0
T7	688652	398	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T23	0	9251	0	0
T26	0	9068	0	0
T38	0	1880	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	547783	0	0
T3	175606	4771	0	0
T6	694998	1486	0	0
T7	688652	398	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T23	0	9251	0	0
T26	0	9068	0	0
T38	0	1880	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	359562642	0	0
T1	1	0	0	0
T2	3297	3296	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T9	2410	2398	0	0
T10	538023	447456	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T13	0	52032	0	0
T14	0	32	0	0
T15	4103	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410997401	547783	0	0
T3	175606	4771	0	0
T6	694998	1486	0	0
T7	688652	398	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T15	4103	0	0	0
T17	73410	0	0	0
T18	0	9369	0	0
T19	0	6	0	0
T20	0	4245	0	0
T23	0	9251	0	0
T26	0	9068	0	0
T38	0	1880	0	0
T46	0	1985	0	0
T47	2209	0	0	0
T48	346178	0	0	0
T49	696	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T6,T7
1	0	Covered	T5,T1,T2

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Covered	T5,T1,T2

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T5,T1,T2
0	0	1	Unreachable
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T2
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2010348469	2010212750	0	0
CheckNGreaterZero_A	1613	1613	0	0
GntImpliesReady_A	2010348469	11728080	0	0
GntImpliesValid_A	2010348469	11728080	0	0
GrantKnown_A	2010348469	2010212750	0	0
IdxKnown_A	2010348469	2010212750	0	0
IndexIsCorrect_A	2010348469	11728080	0	0
LockArbDecision_A	2010348469	0	0	0
NoReadyValidNoGrant_A	2010348469	0	0	0
ReadyAndValidImplyGrant_A	2010348469	11728080	0	0
ReqAndReadyImplyGrant_A	2010348469	11728080	0	0
ReqImpliesValid_A	2010348469	11728080	0	0
ReqStaysHighUntilGranted0_M	2010348469	0	0	0
RoundRobin_A	2010348469	0	0	1613
ValidKnown_A	2010348469	2010212750	0	0
gen_data_port_assertion.DataFlow_A	2010348469	11728080	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1613	1613	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	11728080	0	0
T1	1019	4	0	0
T2	38590	206	0	0
T3	122489	19642	0	0
T5	38636	1024	0	0
T6	362548	19768	0	0
T8	1383	4	0	0
T9	0	134	0	0
T11	298159	2048	0	0
T12	0	1024	0	0
T15	2769	0	0	0
T34	0	3	0	0
T35	1138	0	0	0
T36	1666	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	11728080	0	0
T1	1019	4	0	0
T2	38590	206	0	0
T3	122489	19642	0	0
T5	38636	1024	0	0
T6	362548	19768	0	0
T8	1383	4	0	0
T9	0	134	0	0
T11	298159	2048	0	0
T12	0	1024	0	0
T15	2769	0	0	0
T34	0	3	0	0
T35	1138	0	0	0
T36	1666	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	11728080	0	0
T1	1019	4	0	0
T2	38590	206	0	0
T3	122489	19642	0	0
T5	38636	1024	0	0
T6	362548	19768	0	0
T8	1383	4	0	0
T9	0	134	0	0
T11	298159	2048	0	0
T12	0	1024	0	0
T15	2769	0	0	0
T34	0	3	0	0
T35	1138	0	0	0
T36	1666	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	11728080	0	0
T1	1019	4	0	0
T2	38590	206	0	0
T3	122489	19642	0	0
T5	38636	1024	0	0
T6	362548	19768	0	0
T8	1383	4	0	0
T9	0	134	0	0
T11	298159	2048	0	0
T12	0	1024	0	0
T15	2769	0	0	0
T34	0	3	0	0
T35	1138	0	0	0
T36	1666	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	11728080	0	0
T1	1019	4	0	0
T2	38590	206	0	0
T3	122489	19642	0	0
T5	38636	1024	0	0
T6	362548	19768	0	0
T8	1383	4	0	0
T9	0	134	0	0
T11	298159	2048	0	0
T12	0	1024	0	0
T15	2769	0	0	0
T34	0	3	0	0
T35	1138	0	0	0
T36	1666	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	11728080	0	0
T1	1019	4	0	0
T2	38590	206	0	0
T3	122489	19642	0	0
T5	38636	1024	0	0
T6	362548	19768	0	0
T8	1383	4	0	0
T9	0	134	0	0
T11	298159	2048	0	0
T12	0	1024	0	0
T15	2769	0	0	0
T34	0	3	0	0
T35	1138	0	0	0
T36	1666	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	0	0	1613

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	2010212750	0	0
T1	1019	920	0	0
T2	38590	38523	0	0
T3	122489	122488	0	0
T4	2005	1905	0	0
T5	38636	38549	0	0
T8	1383	1296	0	0
T11	298159	298063	0	0
T15	2769	2719	0	0
T35	1138	1070	0	0
T36	1666	1602	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010348469	11728080	0	0
T1	1019	4	0	0
T2	38590	206	0	0
T3	122489	19642	0	0
T5	38636	1024	0	0
T6	362548	19768	0	0
T8	1383	4	0	0
T9	0	134	0	0
T11	298159	2048	0	0
T12	0	1024	0	0
T15	2769	0	0	0
T34	0	3	0	0
T35	1138	0	0	0
T36	1666	0	0	0

Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T9,T10

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T8
1	0	Covered	T2,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T1

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Unreachable
1	1	Covered	T1,T2,T8

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T8
0	0	1	Unreachable
0	0	0	Covered	T5,T1,T2

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1616209412	1576184653	0	0
CheckNGreaterZero_A	1613	1613	0	0
GntImpliesReady_A	1616209412	9244562	0	0
GntImpliesValid_A	1616209412	9244562	0	0
GrantKnown_A	1616209412	1576184653	0	0
IdxKnown_A	1616209412	1576184653	0	0
IndexIsCorrect_A	1616209412	9244562	0	0
LockArbDecision_A	1616209412	0	0	0
NoReadyValidNoGrant_A	1616209412	0	0	0
ReadyAndValidImplyGrant_A	1616209412	9244562	0	0
ReqAndReadyImplyGrant_A	1616209412	9244562	0	0
ReqImpliesValid_A	1616209412	9244562	0	0
ReqStaysHighUntilGranted0_M	1616209412	0	0	0
RoundRobin_A	1616209412	820	0	718
ValidKnown_A	1616209412	1576184653	0	0
gen_data_port_assertion.DataFlow_A	1616209412	9244562	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	1576184653	0	0
T1	909	909	0	0
T2	38509	38509	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T8	1284	1284	0	0
T9	0	8452	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T15	4103	0	0	0
T34	792	792	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1613	1613	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	9244562	0	0
T1	909	2	0	0
T2	38509	330	0	0
T3	175606	0	0	0
T6	694998	0	0	0
T8	1284	2	0	0
T9	8452	134	0	0
T10	0	27966	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	4103	0	0	0
T33	0	43136	0	0
T34	792	2	0	0
T45	0	29210	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	9244562	0	0
T1	909	2	0	0
T2	38509	330	0	0
T3	175606	0	0	0
T6	694998	0	0	0
T8	1284	2	0	0
T9	8452	134	0	0
T10	0	27966	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	4103	0	0	0
T33	0	43136	0	0
T34	792	2	0	0
T45	0	29210	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	1576184653	0	0
T1	909	909	0	0
T2	38509	38509	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T8	1284	1284	0	0
T9	0	8452	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T15	4103	0	0	0
T34	792	792	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	1576184653	0	0
T1	909	909	0	0
T2	38509	38509	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T8	1284	1284	0	0
T9	0	8452	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T15	4103	0	0	0
T34	792	792	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	9244562	0	0
T1	909	2	0	0
T2	38509	330	0	0
T3	175606	0	0	0
T6	694998	0	0	0
T8	1284	2	0	0
T9	8452	134	0	0
T10	0	27966	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	4103	0	0	0
T33	0	43136	0	0
T34	792	2	0	0
T45	0	29210	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	9244562	0	0
T1	909	2	0	0
T2	38509	330	0	0
T3	175606	0	0	0
T6	694998	0	0	0
T8	1284	2	0	0
T9	8452	134	0	0
T10	0	27966	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	4103	0	0	0
T33	0	43136	0	0
T34	792	2	0	0
T45	0	29210	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	9244562	0	0
T1	909	2	0	0
T2	38509	330	0	0
T3	175606	0	0	0
T6	694998	0	0	0
T8	1284	2	0	0
T9	8452	134	0	0
T10	0	27966	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	4103	0	0	0
T33	0	43136	0	0
T34	792	2	0	0
T45	0	29210	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	9244562	0	0
T1	909	2	0	0
T2	38509	330	0	0
T3	175606	0	0	0
T6	694998	0	0	0
T8	1284	2	0	0
T9	8452	134	0	0
T10	0	27966	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	4103	0	0	0
T33	0	43136	0	0
T34	792	2	0	0
T45	0	29210	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	820	0	718
T7	289527	0	0	1
T17	73410	0	0	0
T23	0	0	0	0
T37	25826	0	0	0
T38	735204	0	0	0
T40	393588	1	0	1
T41	8208	0	0	0
T46	0	0	0	0
T47	16712	0	0	1
T48	328662	0	0	1
T49	696	0	0	0
T50	0	1	0	1
T51	0	1	0	1
T52	0	68	0	0
T53	0	3	0	0
T54	0	6	0	0
T55	0	1	0	0
T56	0	4	0	0
T57	0	6	0	0
T58	0	11	0	0
T59	112403	0	0	1
T60	0	0	0	0
T61	0	0	0	1
T62	0	0	0	1
T63	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	1576184653	0	0
T1	909	909	0	0
T2	38509	38509	0	0
T3	175606	159024	0	0
T5	35200	35200	0	0
T6	694998	663096	0	0
T8	1284	1284	0	0
T9	0	8452	0	0
T11	92864	91593	0	0
T12	48385	48000	0	0
T15	4103	0	0	0
T34	792	792	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1616209412	9244562	0	0
T1	909	2	0	0
T2	38509	330	0	0
T3	175606	0	0	0
T6	694998	0	0	0
T8	1284	2	0	0
T9	8452	134	0	0
T10	0	27966	0	0
T11	92864	0	0	0
T12	48385	0	0	0
T13	0	3252	0	0
T14	0	3	0	0
T15	4103	0	0	0
T33	0	43136	0	0
T34	792	2	0	0
T45	0	29210	0	0