Unified Coverage Report :: Module :: prim_sram_arbiter

Module : prim_sram_arbiter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	66.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter	66.67	100.00	33.33
tb.dut.u_fwmode.u_fwmode_arb	83.33	100.00	66.67
tb.dut.u_sys_sram_arbiter	83.33	100.00	66.67

---

Module Instance : tb.dut.u_upload.u_arbiter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67	100.00	33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.57	92.21	51.22			71.43	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.70	100.00	87.18		100.00	96.30	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
u_req_fifo	60.72	85.00	42.31			55.56	60.00

---

Module Instance : tb.dut.u_fwmode.u_fwmode_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.22	100.00	70.73			96.43	85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.83	91.67	100.00					u_fwmode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25
u_req_fifo	89.96	100.00	65.38			94.44	100.00

---

Module Instance : tb.dut.u_sys_sram_arbiter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.03	100.00	70.73			96.43	80.95

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
u_req_fifo	89.96	100.00	65.38			94.44	100.00

Line Coverage for Module : prim_sram_arbiter ( parameter N=2,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=0 )
Line Coverage for Module self-instances :

SCORE	LINE
83.33	100.00

tb.dut.u_fwmode.u_fwmode_arb

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	0	0
ALWAYS	76	4	4	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	2	2
67	1	1
68	1	1
69	1	1
70		unreachable
76	1	1
77	1	1
78	1	1
80	1	1
125	1	1
147	1	1
150	2	2
151	2	2

---

Line Coverage for Module : prim_sram_arbiter ( parameter N=3,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :

SCORE	LINE
66.67	100.00

tb.dut.u_upload.u_arbiter

SCORE	LINE
83.33	100.00

tb.dut.u_sys_sram_arbiter

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	3	3
67	1	1
68	1	1
69	1	1
70	1	1
125	1	1
147	1	1
150	3	3
151	3	3

---

Cond Coverage for Module : prim_sram_arbiter

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_arbiter

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	3	3
67	1	1
68	1	1
69	1	1
70	1	1
125	1	1
147	1	1
150	3	3
151	3	3

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter

	Total	Covered	Percent
Conditions	6	2	33.33
Logical	6	2	33.33
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T6,T7
1	1	Not Covered

Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	0	0
ALWAYS	76	4	4	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	2	2
67	1	1
68	1	1
69	1	1
70		unreachable
76	1	1
77	1	1
78	1	1
80	1	1
125	1	1
147	1	1
150	2	2
151	2	2

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T8

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T9,T10
1	1	Covered	T1,T2,T8

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	3	3
67	1	1
68	1	1
69	1	1
70	1	1
125	1	1
147	1	1
150	3	3
151	3	3

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T2,T3,T6

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T2,T3,T6