Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	211590	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

190682

1

T1

3072

T2

191

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	281728	1			T1	1025		T2	67		T3	11
values[0x0]	59215	1			T1	1001		T2	85		T3	8
values[0x1]	61329	1			T1	1046		T2	194		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148518	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

253754

1

T1

3072

T2

291

T3

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1414	1			T1	11		T2	1		T8	5
valid_sources[0x01]	1334	1			T1	13		T8	4		T11	48
valid_sources[0x02]	1657	1			T1	14		T8	7		T7	128
valid_sources[0x03]	1210	1			T1	17		T2	1		T11	37
valid_sources[0x04]	1367	1			T1	13		T2	1		T8	5
valid_sources[0x05]	1591	1			T1	15		T2	3		T8	2
valid_sources[0x06]	1478	1			T1	14		T2	3		T3	1
valid_sources[0x07]	1253	1			T1	15		T2	2		T8	6
valid_sources[0x08]	1705	1			T1	14		T8	5		T14	3
valid_sources[0x09]	1733	1			T1	13		T2	1		T8	4
valid_sources[0x0a]	1375	1			T1	6		T2	2		T8	6
valid_sources[0x0b]	1718	1			T1	16		T8	8		T11	47
valid_sources[0x0c]	1710	1			T1	7		T8	5		T4	1
valid_sources[0x0d]	1322	1			T1	8		T2	4		T8	4
valid_sources[0x0e]	1400	1			T1	15		T2	2		T8	6
valid_sources[0x0f]	1188	1			T1	15		T2	3		T8	9
valid_sources[0x10]	1267	1			T1	15		T2	3		T8	2
valid_sources[0x11]	1145	1			T1	10		T2	2		T8	4
valid_sources[0x12]	1337	1			T1	14		T8	5		T14	38
valid_sources[0x13]	1863	1			T1	17		T2	2		T8	9
valid_sources[0x14]	2368	1			T1	15		T2	2		T3	1
valid_sources[0x15]	1599	1			T1	13		T2	2		T8	4
valid_sources[0x16]	1461	1			T1	5		T8	9		T4	1
valid_sources[0x17]	1151	1			T1	11		T2	1		T8	7
valid_sources[0x18]	1418	1			T1	14		T2	3		T8	7
valid_sources[0x19]	1239	1			T1	10		T2	3		T8	4
valid_sources[0x1a]	1599	1			T1	15		T2	1		T8	5
valid_sources[0x1b]	1280	1			T1	7		T2	2		T8	3
valid_sources[0x1c]	1742	1			T1	6		T2	3		T8	5
valid_sources[0x1d]	1308	1			T1	14		T8	5		T14	35
valid_sources[0x1e]	1676	1			T1	16		T2	3		T8	6
valid_sources[0x1f]	1806	1			T1	19		T3	1		T8	8
valid_sources[0x20]	1813	1			T1	9		T2	1		T3	1
valid_sources[0x21]	1101	1			T1	10		T2	2		T8	4
valid_sources[0x22]	1550	1			T1	15		T2	3		T8	6
valid_sources[0x23]	1334	1			T1	10		T2	1		T8	4
valid_sources[0x24]	1394	1			T1	15		T3	1		T8	7
valid_sources[0x25]	1321	1			T1	14		T2	1		T8	3
valid_sources[0x26]	1214	1			T1	11		T2	3		T8	7
valid_sources[0x27]	1471	1			T1	11		T2	1		T8	8
valid_sources[0x28]	1173	1			T1	10		T2	1		T8	5
valid_sources[0x29]	1476	1			T1	10		T2	2		T8	7
valid_sources[0x2a]	1569	1			T1	15		T2	2		T8	5
valid_sources[0x2b]	1549	1			T1	17		T8	3		T14	23
valid_sources[0x2c]	1350	1			T1	12		T2	2		T8	8
valid_sources[0x2d]	1910	1			T1	13		T2	2		T8	5
valid_sources[0x2e]	1192	1			T1	18		T2	3		T8	3
valid_sources[0x2f]	1433	1			T1	12		T8	3		T7	128
valid_sources[0x30]	1485	1			T1	9		T2	4		T8	2
valid_sources[0x31]	1309	1			T1	13		T2	1		T8	5
valid_sources[0x32]	1824	1			T1	7		T2	2		T8	6
valid_sources[0x33]	1380	1			T1	12		T8	5		T4	2
valid_sources[0x34]	1143	1			T1	13		T8	8		T11	14
valid_sources[0x35]	1161	1			T1	19		T2	3		T8	3
valid_sources[0x36]	1365	1			T1	12		T2	1		T8	5
valid_sources[0x37]	1403	1			T1	12		T8	5		T7	128
valid_sources[0x38]	1362	1			T1	14		T2	1		T8	2
valid_sources[0x39]	1375	1			T1	9		T2	1		T8	3
valid_sources[0x3a]	1342	1			T1	17		T8	5		T15	41
valid_sources[0x3b]	1239	1			T1	11		T2	2		T8	2
valid_sources[0x3c]	1393	1			T1	18		T8	5		T11	52
valid_sources[0x3d]	1351	1			T1	18		T2	1		T8	12
valid_sources[0x3e]	1564	1			T1	7		T2	1		T8	8
valid_sources[0x3f]	1731	1			T1	16		T2	1		T8	6
valid_sources[0x40]	1272	1			T1	15		T2	2		T8	2
valid_sources[0x41]	1521	1			T1	13		T2	1		T8	2
valid_sources[0x42]	1860	1			T1	8		T2	2		T8	3
valid_sources[0x43]	1431	1			T1	15		T2	2		T8	6
valid_sources[0x44]	1567	1			T1	9		T8	5		T14	24
valid_sources[0x45]	1218	1			T1	14		T8	8		T11	11
valid_sources[0x46]	1078	1			T1	12		T2	1		T8	3
valid_sources[0x47]	1351	1			T1	11		T2	1		T3	1
valid_sources[0x48]	1303	1			T1	14		T2	1		T8	4
valid_sources[0x49]	1820	1			T1	14		T2	4		T8	9
valid_sources[0x4a]	1352	1			T1	9		T8	5		T14	1
valid_sources[0x4b]	2195	1			T1	16		T2	3		T8	6
valid_sources[0x4c]	1356	1			T1	19		T2	1		T8	5
valid_sources[0x4d]	1292	1			T1	13		T2	3		T8	8
valid_sources[0x4e]	1357	1			T1	18		T2	1		T8	4
valid_sources[0x4f]	2119	1			T1	12		T2	2		T8	7
valid_sources[0x50]	1736	1			T1	19		T2	1		T8	3
valid_sources[0x51]	2112	1			T1	11		T3	1		T8	8
valid_sources[0x52]	1794	1			T1	14		T2	1		T3	1
valid_sources[0x53]	1382	1			T1	12		T2	1		T8	3
valid_sources[0x54]	1942	1			T1	11		T8	4		T14	34
valid_sources[0x55]	1434	1			T1	14		T2	1		T8	5
valid_sources[0x56]	1449	1			T1	5		T2	2		T8	8
valid_sources[0x57]	1199	1			T1	12		T8	5		T11	62
valid_sources[0x58]	1391	1			T1	12		T8	6		T11	52
valid_sources[0x59]	1883	1			T1	19		T8	7		T14	95
valid_sources[0x5a]	1494	1			T1	14		T2	1		T3	1
valid_sources[0x5b]	1112	1			T1	14		T8	1		T4	2
valid_sources[0x5c]	1647	1			T1	6		T2	2		T8	6
valid_sources[0x5d]	1377	1			T1	13		T2	2		T8	2
valid_sources[0x5e]	1205	1			T1	13		T2	1		T8	6
valid_sources[0x5f]	1434	1			T1	9		T8	2		T4	2
valid_sources[0x60]	1249	1			T1	11		T2	3		T8	5
valid_sources[0x61]	1541	1			T1	8		T2	1		T8	3
valid_sources[0x62]	1759	1			T1	18		T2	3		T8	6
valid_sources[0x63]	1882	1			T1	12		T2	1		T8	7
valid_sources[0x64]	1683	1			T1	11		T8	13		T11	64
valid_sources[0x65]	1604	1			T1	7		T2	2		T3	1
valid_sources[0x66]	1218	1			T1	10		T8	8		T11	47
valid_sources[0x67]	1325	1			T1	15		T2	1		T8	8
valid_sources[0x68]	1357	1			T1	8		T2	1		T8	4
valid_sources[0x69]	1572	1			T1	13		T2	1		T8	2
valid_sources[0x6a]	1527	1			T1	9		T8	8		T7	128
valid_sources[0x6b]	1385	1			T1	11		T2	1		T8	4
valid_sources[0x6c]	1447	1			T1	20		T2	1		T8	5
valid_sources[0x6d]	1646	1			T1	9		T2	3		T8	5
valid_sources[0x6e]	2107	1			T1	7		T2	1		T8	4
valid_sources[0x6f]	1206	1			T1	11		T2	2		T8	3
valid_sources[0x70]	1457	1			T1	13		T2	1		T8	5
valid_sources[0x71]	1524	1			T1	14		T2	2		T8	4
valid_sources[0x72]	1640	1			T1	7		T2	4		T3	1
valid_sources[0x73]	1581	1			T1	10		T2	1		T8	3
valid_sources[0x74]	1319	1			T1	6		T2	3		T8	3
valid_sources[0x75]	1710	1			T1	7		T2	2		T3	1
valid_sources[0x76]	1500	1			T1	9		T2	1		T8	1
valid_sources[0x77]	1313	1			T1	6		T2	1		T8	7
valid_sources[0x78]	2701	1			T1	13		T8	2		T14	42
valid_sources[0x79]	2036	1			T1	9		T2	1		T8	4
valid_sources[0x7a]	1964	1			T1	10		T2	2		T3	1
valid_sources[0x7b]	1675	1			T1	14		T2	2		T8	10
valid_sources[0x7c]	1238	1			T1	10		T2	2		T8	4
valid_sources[0x7d]	1584	1			T1	10		T8	5		T14	25
valid_sources[0x7e]	1728	1			T1	10		T2	2		T8	4
valid_sources[0x7f]	1192	1			T1	8		T8	5		T14	5
valid_sources[0x80]	1660	1			T1	8		T2	4		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81694

1

T1

1025

T2

59

T3

3

values[0x0]

all_enables

biggest_size

55280

1

T1

1001

T2

72

T3

5

values[0x1]

all_enables

biggest_size

53708

1

T1

1046

T2

60

T3

2