Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

234384

1

T2

1478

T3

12

T8

1031

full_word

191963

1

T1

3072

T2

283

T3

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	425927	1			T1	3072		T2	1761		T3	22
auto[TlIntgErrCmd]	145	1			T47	6		T19	8		T20	2
auto[TlIntgErrData]	144	1			T47	9		T19	10		T20	3
auto[TlIntgErrBoth]	131	1			T47	5		T19	12		T20	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

284254

1

T1

1025

T2

206

T3

11

auto[1]

142093

1

T1

2047

T2

1555

T3

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	202168	1			T2	136		T3	8		T8	1011
auto[TlIntgErrNone]	partial	auto[1]	31837	1			T2	1342		T3	4		T8	20
auto[TlIntgErrNone]	full_word	auto[0]	81895	1			T1	1025		T2	70		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	110027	1			T1	2047		T2	213		T3	7
auto[TlIntgErrCmd]	partial	auto[0]	64	1			T47	4		T19	2		T20	1
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T47	1		T19	4		T20	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T47	1		T23	1		T66	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T19	2		T23	1		T66	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T47	3		T19	5		T20	1
auto[TlIntgErrData]	partial	auto[1]	68	1			T47	3		T19	5		T20	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T47	1		T66	1		T65	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T47	2		T20	1		T28	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T47	3		T19	3		T20	5
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T47	2		T19	8		T28	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T23	1		T65	1		T67	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T19	1		T23	1		T68	1