Unified Coverage Report :: Module :: prim_generic_clock_buf

Module : prim_generic_clock_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clk_spi_in_buf.gen_generic.u_impl_generic	0.00	0.00
tb.dut.u_clk_spi_out_buf.gen_generic.u_impl_generic	0.00	0.00
tb.dut.u_clk_csb_buf.gen_generic.u_impl_generic	0.00	0.00

---

Module Instance : tb.dut.u_clk_spi_in_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_spi_in_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_spi_out_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_spi_out_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_csb_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_csb_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_buf

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	20	1	0	0.00
CONT_ASSIGN	21	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	0	1
21	0	1

Line Coverage for Instance : tb.dut.u_clk_spi_in_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	20	1	0	0.00
CONT_ASSIGN	21	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	0	1
21	0	1

Line Coverage for Instance : tb.dut.u_clk_spi_out_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	20	1	0	0.00
CONT_ASSIGN	21	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	0	1
21	0	1

Line Coverage for Instance : tb.dut.u_clk_csb_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	20	1	0	0.00
CONT_ASSIGN	21	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' or '../src/lowrisc_prim_generic_clock_buf_0/rtl/prim_generic_clock_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	0	1
21	0	1