Unified Coverage Report :: Module :: prim_generic_ram_2p

Module : prim_generic_ram_2p

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic	0.00	0.00				0.00

---

Module Instance : tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_generic_ram_2p

	Line No.	Total	Covered	Percent
TOTAL		21	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	60	1	0	0.00
CONT_ASSIGN	60	1	0	0.00
CONT_ASSIGN	60	1	0	0.00
CONT_ASSIGN	60	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
CONT_ASSIGN	61	1	0	0.00
ALWAYS	76	6	0	0.00
ALWAYS	91	6	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv' or '../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	0	1
60	0	4
61	0	4
76	0	1
77	0	1
78	0	1
79	0	1
80	0	1
			==> MISSING_ELSE
85	0	1
			==> MISSING_ELSE
91	0	1
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE
100	0	1
			==> MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_2p

	Line No.	Total	Covered	Percent
Branches		6	0	0.00
IF	76	3	0	0.00
IF	91	3	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv' or '../src/lowrisc_prim_generic_ram_2p_0/rtl/prim_generic_ram_2p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if (a_req_i)
-2-:	77	if (a_write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	91	if (b_req_i)
-2-:	92	if (b_write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered