Unified Coverage Report :: Module :: spid_status

Module : spid_status

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_status	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_spid_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
19.21	0.00	0.00	76.82		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_stage_to_commit	0.00	0.00				0.00
u_sw_status_update_sync	0.00	0.00	0.00			0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_status

	Line No.	Total	Covered	Percent
TOTAL		60	0	0.00
CONT_ASSIGN	70	1	0	0.00
CONT_ASSIGN	73	1	0	0.00
ALWAYS	140	6	0	0.00
ALWAYS	151	8	0	0.00
ALWAYS	164	4	0	0.00
CONT_ASSIGN	182	1	0	0.00
ALWAYS	211	4	0	0.00
ALWAYS	224	5	0	0.00
ALWAYS	238	3	0	0.00
ALWAYS	246	11	0	0.00
CONT_ASSIGN	267	1	0	0.00
ALWAYS	274	3	0	0.00
ALWAYS	279	12	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
70	0	1
73	0	1
140	0	1
141	0	1
142	0	1
143	0	1
144	0	1
145	0	1
			==> MISSING_ELSE
151	0	1
152	0	1
153	0	1
154	0	1
155	0	1
156	0	1
157	0	1
158	0	1
			==> MISSING_ELSE
164	0	1
165	0	1
166	0	1
167	0	1
			==> MISSING_ELSE
182	0	1
211	0	1
212	0	1
213	0	1
214	0	1
			==> MISSING_ELSE
224	0	1
225	0	1
226	0	1
228	0	1
229	0	1
238	0	1
239	0	1
241	0	1
246	0	1
248	0	1
250	0	1
252	0	1
253	0	1
254	0	1
			==> MISSING_ELSE
257	0	1
258	0	1
259	0	1
260	0	1
261	0	1
			==> MISSING_ELSE
267	0	1
274	0	2
275	0	1
279	0	1
281	0	1
282	0	1
284	0	1
286	0	1
288	0	1
289	0	1
291	0	1
292	0	1
			==> MISSING_ELSE
297	0	1
305	0	2
			==> MISSING_ELSE

---

Cond Coverage for Module : spid_status

	Total	Covered	Percent
Conditions	13	0	0.00
Logical	13	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       142
 EXPRESSION (sck_sw_we && (sck_sw_status[BitBusy] == 1'b0))
             ----1----    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       142
 SUB-EXPRESSION (sck_sw_status[BitBusy] == 1'b0)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       253
 EXPRESSION (cmd_info_idx_i == 5'(StatusCmdIdx[i]))
            -------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       267
 EXPRESSION ((st_q == StIdle) ? sck_status_committed[(8 * byte_sel_d)+:8] : sck_status_committed[(8 * byte_sel_q)+:8])
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       267
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       288
 EXPRESSION (sel_dp_i == DpReadStatus)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : spid_status

Summary for FSM :: byte_sel_q

	Total	Covered	Percent
States	3	0	0.00	(Not included in score)
Transitions	4	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: byte_sel_q

---

states	Line No.	Covered	Tests
'h0	250	Not Covered
'h1	259	Not Covered
'h2	260	Not Covered

transitions	Line No.	Covered	Tests
'h0->'h1	259	Not Covered
'h1->'h0	250	Not Covered
'h1->'h2	260	Not Covered
'h2->'h0	250	Not Covered

---

Branch Coverage for Module : spid_status

	Line No.	Total	Covered	Percent
Branches		34	0	0.00
TERNARY	267	2	0	0.00
IF	140	4	0	0.00
IF	151	5	0	0.00
IF	164	3	0	0.00
IF	211	3	0	0.00
IF	224	2	0	0.00
IF	238	2	0	0.00
IF	248	6	0	0.00
IF	274	2	0	0.00
CASE	286	5	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_status.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	267	((st_q == StIdle)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	140	if ((!sys_rst_ni))
-2-:	142	if ((sck_sw_we && (sck_sw_status[BitBusy] == 1'b0)))
-3-:	144	if (inclk_busy_set_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	151	if ((!sys_rst_ni))
-2-:	153	if (inclk_we_set_i)
-3-:	155	if (inclk_we_clr_i)
-4-:	157	if (sck_sw_we)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	164	if ((!sys_rst_ni))
-2-:	166	if (sck_sw_we)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	211	if ((!sys_rst_ni))
-2-:	213	if (sys_csb_deasserted_pulse_i)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	224	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	238	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	248	if (byte_sel_update)
-2-:	257	if (byte_sel_inc)
-3-:	258	case (byte_sel_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	2'b00	Not Covered
0	1	2'b01	Not Covered
0	1	2'b10	Not Covered
0	1	default	Not Covered
0	0	-	Not Covered

	LineNo.	Expression
-1-:	274	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	case (st_q)
-2-:	288	if ((sel_dp_i == DpReadStatus))
-3-:	305	if (outclk_p2s_sent_i)

Branches:

-1-	-2-	-3-	Status	Tests
StIdle	1	-	Not Covered
StIdle	0	-	Not Covered
StActive	-	1	Not Covered
StActive	-	0	Not Covered
default	-	-	Not Covered