Unified Coverage Report :: Module :: spi_fwm_txf_ctrl

Module : spi_fwm_txf_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_txf_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_fwmode.u_txf_ctrl	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_fwmode.u_txf_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00					u_fwmode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_fwm_txf_ctrl

	Line No.	Total	Covered	Percent
TOTAL		82	0	0.00
ALWAYS	80	3	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	86	1	0	0.00
CONT_ASSIGN	88	1	0	0.00
ALWAYS	93	38	0	0.00
ALWAYS	162	6	0	0.00
ALWAYS	174	4	0	0.00
ALWAYS	182	11	0	0.00
ALWAYS	204	3	0	0.00
CONT_ASSIGN	213	1	0	0.00
CONT_ASSIGN	218	1	0	0.00
ALWAYS	223	3	0	0.00
ALWAYS	228	4	0	0.00
CONT_ASSIGN	232	1	0	0.00
ALWAYS	235	4	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_txf_ctrl.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_txf_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	0	2
81	0	1
84	0	1
86	0	1
88	0	1
93	0	1
94	0	1
95	0	1
96	0	1
97	0	1
98	0	1
99	0	1
100	0	1
101	0	1
103	0	1
104	0	1
105	0	1
106	0	1
108	0	1
113	0	1
114	0	1
115	0	1
116	0	1
118	0	1
119	0	1
124	0	1
125	0	1
126	0	1
127	0	1
128	0	1
130	0	1
135	0	1
136	0	1
137	0	1
138	0	1
139	0	1
140	0	1
141	0	1
142	0	1
143	0	1
146	0	1
151	0	1
152	0	1
162	0	1
163	0	1
164	0	1
166	0	1
167	0	1
169	0	1
			==> MISSING_ELSE
174	0	1
175	0	1
176	0	1
177	0	1
			==> MISSING_ELSE
182	0	1
183	0	1
184	0	1
185	0	1
187	0	1
188	0	1
189	0	1
191	0	1
192	0	1
193	0	1
197	0	1
			==> MISSING_ELSE
204	0	1
206	0	1
208	0	1
213	0	1
218	0	1
223	0	2
224	0	1
228	0	2
229	0	2
			==> MISSING_ELSE
232	0	1
235	0	1
236	0	1
237	0	2
			==> MISSING_ELSE

---

Cond Coverage for Module : spi_fwm_txf_ctrl

	Total	Covered	Percent
Conditions	29	0	0.00
Logical	29	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       84
 EXPRESSION (spi_mode_i == FwMode)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       86
 EXPRESSION (rptr == wptr_q)
            --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       104
 EXPRESSION (active && ((!sramf_empty)) && fifo_ready)
             ---1--    --------2-------    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       139
 EXPRESSION (fifo_ready && ((!cnt_eq_end)))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       185
 EXPRESSION (pos == '0)
            -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       187
 EXPRESSION (rptr[(PtrW - 2):SDW] != sramf_limit)
            ------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       204
 EXPRESSION (wptr[(PtrW - 1)] == rptr[(PtrW - 1)])
            -------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       213
 EXPRESSION ((wptr_q[(PtrW - 1):SDW] == rptr[(PtrW - 1):SDW]) ? (wptr_q[(SDW - 1):0] == pos) : (pos == '0))
             ------------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       213
 SUB-EXPRESSION (wptr_q[(PtrW - 1):SDW] == rptr[(PtrW - 1):SDW])
                ------------------------1-----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       213
 SUB-EXPRESSION (wptr_q[(SDW - 1):0] == pos)
                --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       213
 SUB-EXPRESSION (pos == '0)
                -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       232
 EXPRESSION (txf_sel ? sram_rdata_q : sram_rdata)
             ---1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       237
 EXPRESSION (pos == i[(SDW - 1):0])
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : spi_fwm_txf_ctrl

Summary for FSM :: st

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	5	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StIdle	108	Not Covered
StLatch	114	Not Covered
StPush	125	Not Covered
StRead	105	Not Covered
StUpdate	136	Not Covered

transitions	Line No.	Covered	Tests
StIdle->StRead	105	Not Covered
StLatch->StPush	125	Not Covered
StPush->StUpdate	136	Not Covered
StRead->StLatch	114	Not Covered
StUpdate->StIdle	151	Not Covered

---

Branch Coverage for Module : spi_fwm_txf_ctrl

	Line No.	Total	Covered	Percent
Branches		39	0	0.00
TERNARY	213	2	0	0.00
TERNARY	232	2	0	0.00
IF	80	2	0	0.00
CASE	101	12	0	0.00
IF	162	4	0	0.00
IF	174	3	0	0.00
IF	182	5	0	0.00
IF	204	2	0	0.00
IF	223	2	0	0.00
IF	228	3	0	0.00
IF	237	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_txf_ctrl.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_fwm_txf_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((wptr_q[(PtrW - 1):SDW] == rptr[(PtrW - 1):SDW])) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	232	(txf_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	101	case (st)
-2-:	104	if (((active && (!sramf_empty)) && fifo_ready))
-3-:	113	if (sram_gnt)
-4-:	124	if (sram_rvalid)
-5-:	135	if (abort)
-6-:	137	if ((!fifo_ready))
-7-:	139	if ((fifo_ready && (!cnt_eq_end)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle	1	-	-	-	-	-	Not Covered
StIdle	0	-	-	-	-	-	Not Covered
StRead	-	1	-	-	-	-	Not Covered
StRead	-	0	-	-	-	-	Not Covered
StLatch	-	-	1	-	-	-	Not Covered
StLatch	-	-	0	-	-	-	Not Covered
StPush	-	-	-	1	-	-	Not Covered
StPush	-	-	-	0	1	-	Not Covered
StPush	-	-	-	0	0	1	Not Covered
StPush	-	-	-	0	0	0	Not Covered
StUpdate	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	162	if ((!rst_ni))
-2-:	164	if (cnt_rst)
-3-:	167	if (cnt_incr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	174	if ((!rst_ni))
-2-:	176	if (latch_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	182	if ((!rst_ni))
-2-:	184	if (update_rptr)
-3-:	185	if ((pos == '0))
-4-:	187	if ((rptr[(PtrW - 2):SDW] != sramf_limit))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	1	1	Not Covered
0	1	1	0	Not Covered
0	1	0	-	Not Covered
0	0	-	-	Not Covered

	LineNo.	Expression
-1-:	204	if ((wptr[(PtrW - 1)] == rptr[(PtrW - 1)]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	223	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	228	if ((!rst_ni))
-2-:	229	if (sram_rvalid)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	237	if ((pos == i[(SDW - 1):0]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered