Module Definition
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Module : spi_p2s
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_p2s 0.00 0.00 0.00 0.00



Module Instance : tb.dut.u_p2s

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spi_p2s
Line No.TotalCoveredPercent
TOTAL3700.00
ALWAYS71500.00
CONT_ASSIGN92100.00
ALWAYS111500.00
ALWAYS123400.00
CONT_ASSIGN143100.00
ALWAYS147500.00
CONT_ASSIGN179100.00
ALWAYS183600.00
CONT_ASSIGN192100.00
ALWAYS196500.00
ALWAYS214300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
71 0 1
73 0 1
75 0 1
79 0 1
83 0 1
92 0 1
111 0 1
113 0 1
114 0 1
115 0 1
116 0 1
123 0 1
125 0 1
129 0 1
133 0 1
143 0 1
147 0 1
149 0 1
151 0 1
156 0 1
161 0 1
179 0 1
183 0 1
184 0 1
185 0 1
186 0 1
187 0 1
188 0 1
==> MISSING_ELSE
192 0 1
196 0 1
198 0 1
199 0 1
200 0 1
201 0 1
214 0 1
215 0 1
217 0 1


Cond Coverage for Module : spi_p2s
TotalCoveredPercent
Conditions5200.00
Logical5200.00
Non-Logical00
Event00

 LINE       92
 EXPRESSION (csb_i ? 4'b0 : out_enable)
             --1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       114
 EXPRESSION (cnt == 3'h6)
            ------1------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       115
 EXPRESSION (cnt == 3'h2)
            ------1------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       116
 EXPRESSION (cnt == 3'b0)
            ------1------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       125
 EXPRESSION (order_i ? ({1'b0, out_shift_d[7:1]}) : ({out_shift_d[6:0], 1'b0}))
             ---1---
-1-StatusTests
0Not Covered
1Not Covered

 LINE       129
 EXPRESSION (order_i ? ({2'b0, out_shift_d[7:2]}) : ({out_shift_d[5:0], 2'b0}))
             ---1---
-1-StatusTests
0Not Covered
1Not Covered

 LINE       133
 EXPRESSION (order_i ? ({4'b0, out_shift_d[7:4]}) : ({out_shift_d[3:0], 4'b0}))
             ---1---
-1-StatusTests
0Not Covered
1Not Covered

 LINE       143
 EXPRESSION (first_beat ? data_i : out_shift)
             -----1----
-1-StatusTests
0Not Covered
1Not Covered

 LINE       151
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[0] : data_i[0]) : (((!first_beat)) ? out_shift[7] : data_i[7]))
             ---1---
-1-StatusTests
0Not Covered
1Not Covered

 LINE       151
 SUB-EXPRESSION (((!first_beat)) ? out_shift[0] : data_i[0])
                 -------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       151
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7] : data_i[7])
                 -------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       156
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[1:0] : data_i[1:0]) : (((!first_beat)) ? out_shift[7:6] : data_i[7:6]))
             ---1---
-1-StatusTests
0Not Covered
1Not Covered

 LINE       156
 SUB-EXPRESSION (((!first_beat)) ? out_shift[1:0] : data_i[1:0])
                 -------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       156
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7:6] : data_i[7:6])
                 -------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       161
 EXPRESSION (order_i ? (((!first_beat)) ? out_shift[3:0] : data_i[3:0]) : (((!first_beat)) ? out_shift[7:4] : data_i[7:4]))
             ---1---
-1-StatusTests
0Not Covered
1Not Covered

 LINE       161
 SUB-EXPRESSION (((!first_beat)) ? out_shift[3:0] : data_i[3:0])
                 -------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       161
 SUB-EXPRESSION (((!first_beat)) ? out_shift[7:4] : data_i[7:4])
                 -------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       187
 EXPRESSION (data_valid_i && ((tx_state != TxIdle) || (cpha_i == 1'b0)))
             ------1-----    ---------------------2--------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       187
 SUB-EXPRESSION ((tx_state != TxIdle) || (cpha_i == 1'b0))
                 ----------1---------    --------2-------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       187
 SUB-EXPRESSION (tx_state != TxIdle)
                ----------1---------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       187
 SUB-EXPRESSION (cpha_i == 1'b0)
                --------1-------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       192
 EXPRESSION (cnt == '0)
            -----1-----
-1-StatusTests
0Not Covered
1Not Covered

 LINE       199
 EXPRESSION (cnt == 3'('h00000007))
            -----------1-----------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       200
 EXPRESSION (cnt == 3'('h00000003))
            -----------1-----------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       201
 EXPRESSION (cnt == 3'('b1))
            --------1-------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Module : spi_p2s
Line No.TotalCoveredPercent
Branches 42 0 0.00
TERNARY 92 2 0 0.00
TERNARY 143 2 0 0.00
CASE 73 4 0 0.00
CASE 113 4 0 0.00
CASE 123 7 0 0.00
CASE 149 13 0 0.00
IF 183 4 0 0.00
CASE 198 4 0 0.00
IF 214 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_p2s.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (csb_i) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 143 (first_beat) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 73 case (io_mode)

Branches:
-1-StatusTests
SingleIO Not Covered
DualIO Not Covered
QuadIO Not Covered
default Not Covered


LineNo. Expression -1-: 113 case (io_mode)

Branches:
-1-StatusTests
SingleIO Not Covered
DualIO Not Covered
QuadIO Not Covered
default Not Covered


LineNo. Expression -1-: 123 case (io_mode) -2-: 125 (order_i) ? -3-: 129 (order_i) ? -4-: 133 (order_i) ?

Branches:
-1--2--3--4-StatusTests
SingleIO 1 - - Not Covered
SingleIO 0 - - Not Covered
DualIO - 1 - Not Covered
DualIO - 0 - Not Covered
QuadIO - - 1 Not Covered
QuadIO - - 0 Not Covered
default - - - Not Covered


LineNo. Expression -1-: 149 case (io_mode) -2-: 151 (order_i) ? -3-: 151 ((!first_beat)) ? -4-: 151 ((!first_beat)) ? -5-: 156 (order_i) ? -6-: 156 ((!first_beat)) ? -7-: 156 ((!first_beat)) ? -8-: 161 (order_i) ? -9-: 161 ((!first_beat)) ? -10-: 161 ((!first_beat)) ?

Branches:
-1--2--3--4--5--6--7--8--9--10-StatusTests
SingleIO 1 1 - - - - - - - Not Covered
SingleIO 1 0 - - - - - - - Not Covered
SingleIO 0 - 1 - - - - - - Not Covered
SingleIO 0 - 0 - - - - - - Not Covered
DualIO - - - 1 1 - - - - Not Covered
DualIO - - - 1 0 - - - - Not Covered
DualIO - - - 0 - 1 - - - Not Covered
DualIO - - - 0 - 0 - - - Not Covered
QuadIO - - - - - - 1 1 - Not Covered
QuadIO - - - - - - 1 0 - Not Covered
QuadIO - - - - - - 0 - 1 Not Covered
QuadIO - - - - - - 0 - 0 Not Covered
default - - - - - - - - - Not Covered


LineNo. Expression -1-: 183 if ((!rst_ni)) -2-: 185 if (last_beat) -3-: 187 if ((data_valid_i && ((tx_state != TxIdle) || (cpha_i == 1'b0))))

Branches:
-1--2--3-StatusTests
1 - - Not Covered
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Not Covered


LineNo. Expression -1-: 198 case (io_mode)

Branches:
-1-StatusTests
SingleIO Not Covered
DualIO Not Covered
QuadIO Not Covered
default Not Covered


LineNo. Expression -1-: 214 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%