Unified Coverage Report :: Module :: prim_fifo_async_sram_adapter

Module : prim_fifo_async_sram_adapter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_cmdfifo	0.00	0.00	0.00			0.00
tb.dut.u_upload.u_addrfifo	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_upload.u_cmdfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_rptr_gray	0.00	0.00				0.00
u_sync_wptr_gray	0.00	0.00				0.00

---

Module Instance : tb.dut.u_upload.u_addrfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sync_rptr_gray	0.00	0.00				0.00
u_sync_wptr_gray	0.00	0.00				0.00

Line Coverage for Module : prim_fifo_async_sram_adapter ( parameter Width=8,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=896,DepthW=5,PtrVW=4,PtrW=5 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_upload.u_cmdfifo

	Line No.	Total	Covered	Percent
TOTAL		86	0	0.00
CONT_ASSIGN	121	1	0	0.00
CONT_ASSIGN	123	1	0	0.00
ALWAYS	126	6	0	0.00
CONT_ASSIGN	135	1	0	0.00
CONT_ASSIGN	136	1	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	149	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	153	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	165	1	0	0.00
ALWAYS	168	6	0	0.00
CONT_ASSIGN	177	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	180	1	0	0.00
CONT_ASSIGN	191	1	0	0.00
CONT_ASSIGN	192	1	0	0.00
CONT_ASSIGN	193	1	0	0.00
CONT_ASSIGN	195	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
ALWAYS	204	4	0	0.00
CONT_ASSIGN	211	1	0	0.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	218	1	0	0.00
CONT_ASSIGN	219	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	245	1	0	0.00
CONT_ASSIGN	247	1	0	0.00
CONT_ASSIGN	248	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	252	1	0	0.00
CONT_ASSIGN	254	1	0	0.00
CONT_ASSIGN	256	1	0	0.00
CONT_ASSIGN	260	1	0	0.00
ALWAYS	270	4	0	0.00
CONT_ASSIGN	291	1	0	0.00
CONT_ASSIGN	297	1	0	0.00
CONT_ASSIGN	299	1	0	0.00
CONT_ASSIGN	301	1	0	0.00
CONT_ASSIGN	304	1	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	321	1	0	0.00
ALWAYS	324	9	0	0.00
ROUTINE	347	7	0	0.00
ROUTINE	368	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
121	0	1
123	0	1
126	0	1
127	0	1
128	0	1
129	0	1
130	0	1
131	0	1
			==> MISSING_ELSE
135	0	1
136	0	1
138	0	1
149	0	1
150	0	1
151	0	1
153	0	1
163	0	1
165	0	1
168	0	1
169	0	1
170	0	1
171	0	1
172	0	1
173	0	1
			==> MISSING_ELSE
177	0	1
178	0	1
180	0	1
191	0	1
192	0	1
193	0	1
195	0	1
201	0	1
204	0	1
205	0	1
206	0	1
207	0	1
			==> MISSING_ELSE
211	0	1
217	0	1
218	0	1
219	0	1
222	0	1
224	0	1
225	0	1
245	0	1
247	0	1
248	0	1
251	0	1
252	0	1
254	0	1
256	0	1
260	0	1
270	0	1
279	0	1
282	0	1
287	0	1
291	0	1
297	0	1
299	0	1
301	0	1
304	0	1
308	0	1
321	0	1
324	0	1
325	0	1
326	0	1
327	0	1
328	0	1
329	0	1
330	0	1
332	0	1
333	0	1
			==> MISSING_ELSE
347	0	1
349	0	1
352	0	1
353	0	1
356	0	1
357	0	1
360	0	1
368	0	1
369	0	1
370	0	1
372	0	1
373	0	1
374	0	1
376	0	1
377	0	1
379	0	1

---

Line Coverage for Module : prim_fifo_async_sram_adapter ( parameter Width=32,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=912,DepthW=5,PtrVW=4,PtrW=5 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_upload.u_addrfifo

	Line No.	Total	Covered	Percent
TOTAL		85	0	0.00
CONT_ASSIGN	121	1	0	0.00
CONT_ASSIGN	123	1	0	0.00
ALWAYS	126	6	0	0.00
CONT_ASSIGN	135	1	0	0.00
CONT_ASSIGN	136	1	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	149	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	153	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	165	1	0	0.00
ALWAYS	168	6	0	0.00
CONT_ASSIGN	177	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	180	1	0	0.00
CONT_ASSIGN	191	1	0	0.00
CONT_ASSIGN	192	1	0	0.00
CONT_ASSIGN	193	1	0	0.00
CONT_ASSIGN	195	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
ALWAYS	204	4	0	0.00
CONT_ASSIGN	211	1	0	0.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	218	1	0	0.00
CONT_ASSIGN	219	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	245	1	0	0.00
CONT_ASSIGN	247	1	0	0.00
CONT_ASSIGN	248	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	252	1	0	0.00
CONT_ASSIGN	254	1	0	0.00
CONT_ASSIGN	256	1	0	0.00
CONT_ASSIGN	260	1	0	0.00
ALWAYS	270	4	0	0.00
CONT_ASSIGN	291	1	0	0.00
CONT_ASSIGN	297	1	0	0.00
CONT_ASSIGN	299	1	0	0.00
CONT_ASSIGN	301	1	0	0.00
CONT_ASSIGN	304	1	0	0.00
CONT_ASSIGN	321	1	0	0.00
ALWAYS	324	9	0	0.00
ROUTINE	347	7	0	0.00
ROUTINE	368	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
121	0	1
123	0	1
126	0	1
127	0	1
128	0	1
129	0	1
130	0	1
131	0	1
			==> MISSING_ELSE
135	0	1
136	0	1
138	0	1
149	0	1
150	0	1
151	0	1
153	0	1
163	0	1
165	0	1
168	0	1
169	0	1
170	0	1
171	0	1
172	0	1
173	0	1
			==> MISSING_ELSE
177	0	1
178	0	1
180	0	1
191	0	1
192	0	1
193	0	1
195	0	1
201	0	1
204	0	1
205	0	1
206	0	1
207	0	1
			==> MISSING_ELSE
211	0	1
217	0	1
218	0	1
219	0	1
222	0	1
224	0	1
225	0	1
245	0	1
247	0	1
248	0	1
251	0	1
252	0	1
254	0	1
256	0	1
260	0	1
270	0	1
279	0	1
282	0	1
287	0	1
291	0	1
297	0	1
299	0	1
301	0	1
304	0	1
321	0	1
324	0	1
325	0	1
326	0	1
327	0	1
328	0	1
329	0	1
330	0	1
332	0	1
333	0	1
			==> MISSING_ELSE
347	0	1
349	0	1
352	0	1
353	0	1
356	0	1
357	0	1
360	0	1
368	0	1
369	0	1
370	0	1
372	0	1
373	0	1
374	0	1
376	0	1
377	0	1
379	0	1

---

Cond Coverage for Module : prim_fifo_async_sram_adapter ( parameter Width=8,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=896,DepthW=5,PtrVW=4,PtrW=5 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_upload.u_cmdfifo

	Total	Covered	Percent
Conditions	68	0	0.00
Logical	68	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       121
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       153
 EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       153
 SUB-EXPRESSION (w_wptr_p == w_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       195
 EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       195
 SUB-EXPRESSION (r_wptr_p == r_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       211
 EXPRESSION (r_wptr == r_sram_rptr)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       217
 EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       218
 EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       219
 EXPRESSION (r_wptr == r_rptr_q)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       247
 EXPRESSION (r_sram_req_o && r_sram_gnt_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       248
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       251
 EXPRESSION (wvalid_i && ((!w_full)))
             ----1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       252
 EXPRESSION (((!w_full)) && w_sram_gnt_i)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       282
 EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
             ----------1----------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       287
 EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
             ----------1----------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       287
 SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
                    --------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       287
 SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
                 -------1-------   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       291
 EXPRESSION (stored || r_sram_rvalid_i)
             ---1--    -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       299
 EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (8'(0)))
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       301
 EXPRESSION (stored ? rdata_q : rdata_d)
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       321
 EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
             -------1-------    -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       321
 SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
                    ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       321
 SUB-EXPRESSION (stored ^ rfifo_ack)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       330
 EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       349
 EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       370
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Cond Coverage for Module : prim_fifo_async_sram_adapter ( parameter Width=32,Depth=16,SramAw=10,SramDw=32,SramBaseAddr=912,DepthW=5,PtrVW=4,PtrW=5 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_upload.u_addrfifo

	Total	Covered	Percent
Conditions	68	0	0.00
Logical	68	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       121
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       153
 EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       153
 SUB-EXPRESSION (w_wptr_p == w_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       195
 EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       195
 SUB-EXPRESSION (r_wptr_p == r_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       211
 EXPRESSION (r_wptr == r_sram_rptr)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       217
 EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       218
 EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       219
 EXPRESSION (r_wptr == r_rptr_q)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       247
 EXPRESSION (r_sram_req_o && r_sram_gnt_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       248
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       251
 EXPRESSION (wvalid_i && ((!w_full)))
             ----1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       252
 EXPRESSION (((!w_full)) && w_sram_gnt_i)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       282
 EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
             ----------1----------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       287
 EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
             ----------1----------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       287
 SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
                    --------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       287
 SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
                 -------1-------   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       291
 EXPRESSION (stored || r_sram_rvalid_i)
             ---1--    -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       299
 EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (32'(0)))
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       301
 EXPRESSION (stored ? rdata_q : rdata_d)
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       321
 EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
             -------1-------    -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       321
 SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
                    ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       321
 SUB-EXPRESSION (stored ^ rfifo_ack)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       330
 EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       349
 EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       370
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : prim_fifo_async_sram_adapter

	Line No.	Total	Covered	Percent
Branches		27	0	0.00
TERNARY	153	2	0	0.00
TERNARY	195	2	0	0.00
TERNARY	299	2	0	0.00
TERNARY	301	2	0	0.00
IF	126	3	0	0.00
IF	168	3	0	0.00
IF	204	3	0	0.00
IF	279	2	0	0.00
IF	324	4	0	0.00
TERNARY	349	2	0	0.00
IF	373	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	153	((w_wptr_p == w_rptr_p)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	195	((r_wptr_p == r_rptr_p)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	299	(r_sram_rvalid_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	301	(stored) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	126	if ((!rst_wr_ni))
-2-:	129	if (w_wptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	168	if ((!rst_rd_ni))
-2-:	171	if (r_rptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	204	if ((!rst_rd_ni))
-2-:	206	if (r_sram_rptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	279	if (stored)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	324	if ((!rst_rd_ni))
-2-:	327	if (store_en)
-3-:	330	if (((!r_sram_rvalid_i) && rfifo_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	349	(decval[(PtrW - 1)]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	373	if (grayval[(PtrW - 1)])

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo

	Line No.	Total	Covered	Percent
TOTAL		86	0	0.00
CONT_ASSIGN	121	1	0	0.00
CONT_ASSIGN	123	1	0	0.00
ALWAYS	126	6	0	0.00
CONT_ASSIGN	135	1	0	0.00
CONT_ASSIGN	136	1	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	149	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	153	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	165	1	0	0.00
ALWAYS	168	6	0	0.00
CONT_ASSIGN	177	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	180	1	0	0.00
CONT_ASSIGN	191	1	0	0.00
CONT_ASSIGN	192	1	0	0.00
CONT_ASSIGN	193	1	0	0.00
CONT_ASSIGN	195	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
ALWAYS	204	4	0	0.00
CONT_ASSIGN	211	1	0	0.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	218	1	0	0.00
CONT_ASSIGN	219	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	245	1	0	0.00
CONT_ASSIGN	247	1	0	0.00
CONT_ASSIGN	248	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	252	1	0	0.00
CONT_ASSIGN	254	1	0	0.00
CONT_ASSIGN	256	1	0	0.00
CONT_ASSIGN	260	1	0	0.00
ALWAYS	270	4	0	0.00
CONT_ASSIGN	291	1	0	0.00
CONT_ASSIGN	297	1	0	0.00
CONT_ASSIGN	299	1	0	0.00
CONT_ASSIGN	301	1	0	0.00
CONT_ASSIGN	304	1	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	321	1	0	0.00
ALWAYS	324	9	0	0.00
ROUTINE	347	7	0	0.00
ROUTINE	368	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
121	0	1
123	0	1
126	0	1
127	0	1
128	0	1
129	0	1
130	0	1
131	0	1
			==> MISSING_ELSE
135	0	1
136	0	1
138	0	1
149	0	1
150	0	1
151	0	1
153	0	1
163	0	1
165	0	1
168	0	1
169	0	1
170	0	1
171	0	1
172	0	1
173	0	1
			==> MISSING_ELSE
177	0	1
178	0	1
180	0	1
191	0	1
192	0	1
193	0	1
195	0	1
201	0	1
204	0	1
205	0	1
206	0	1
207	0	1
			==> MISSING_ELSE
211	0	1
217	0	1
218	0	1
219	0	1
222	0	1
224	0	1
225	0	1
245	0	1
247	0	1
248	0	1
251	0	1
252	0	1
254	0	1
256	0	1
260	0	1
270	0	1
279	0	1
282	0	1
287	0	1
291	0	1
297	0	1
299	0	1
301	0	1
304	0	1
308	0	1
321	0	1
324	0	1
325	0	1
326	0	1
327	0	1
328	0	1
329	0	1
330	0	1
332	0	1
333	0	1
			==> MISSING_ELSE
347	0	1
349	0	1
352	0	1
353	0	1
356	0	1
357	0	1
360	0	1
368	0	1
369	0	1
370	0	1
372	0	1
373	0	1
374	0	1
376	0	1
377	0	1
379	0	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_cmdfifo

	Total	Covered	Percent
Conditions	68	0	0.00
Logical	68	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       121
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       153
 EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       153
 SUB-EXPRESSION (w_wptr_p == w_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       195
 EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       195
 SUB-EXPRESSION (r_wptr_p == r_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       211
 EXPRESSION (r_wptr == r_sram_rptr)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       217
 EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       218
 EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       219
 EXPRESSION (r_wptr == r_rptr_q)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       247
 EXPRESSION (r_sram_req_o && r_sram_gnt_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       248
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       251
 EXPRESSION (wvalid_i && ((!w_full)))
             ----1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       252
 EXPRESSION (((!w_full)) && w_sram_gnt_i)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       282
 EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
             ----------1----------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       287
 EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
             ----------1----------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       287
 SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
                    --------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       287
 SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
                 -------1-------   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       291
 EXPRESSION (stored || r_sram_rvalid_i)
             ---1--    -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       299
 EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (8'(0)))
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       301
 EXPRESSION (stored ? rdata_q : rdata_d)
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       321
 EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
             -------1-------    -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       321
 SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
                    ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       321
 SUB-EXPRESSION (stored ^ rfifo_ack)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       330
 EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       349
 EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       370
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo

	Line No.	Total	Covered	Percent
Branches		27	0	0.00
TERNARY	153	2	0	0.00
TERNARY	195	2	0	0.00
TERNARY	299	2	0	0.00
TERNARY	301	2	0	0.00
IF	126	3	0	0.00
IF	168	3	0	0.00
IF	204	3	0	0.00
IF	279	2	0	0.00
IF	324	4	0	0.00
TERNARY	349	2	0	0.00
IF	373	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	153	((w_wptr_p == w_rptr_p)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	195	((r_wptr_p == r_rptr_p)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	299	(r_sram_rvalid_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	301	(stored) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	126	if ((!rst_wr_ni))
-2-:	129	if (w_wptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	168	if ((!rst_rd_ni))
-2-:	171	if (r_rptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	204	if ((!rst_rd_ni))
-2-:	206	if (r_sram_rptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	279	if (stored)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	324	if ((!rst_rd_ni))
-2-:	327	if (store_en)
-3-:	330	if (((!r_sram_rvalid_i) && rfifo_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	349	(decval[(PtrW - 1)]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	373	if (grayval[(PtrW - 1)])

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_upload.u_addrfifo

	Line No.	Total	Covered	Percent
TOTAL		85	0	0.00
CONT_ASSIGN	121	1	0	0.00
CONT_ASSIGN	123	1	0	0.00
ALWAYS	126	6	0	0.00
CONT_ASSIGN	135	1	0	0.00
CONT_ASSIGN	136	1	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	149	1	0	0.00
CONT_ASSIGN	150	1	0	0.00
CONT_ASSIGN	151	1	0	0.00
CONT_ASSIGN	153	1	0	0.00
CONT_ASSIGN	163	1	0	0.00
CONT_ASSIGN	165	1	0	0.00
ALWAYS	168	6	0	0.00
CONT_ASSIGN	177	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	180	1	0	0.00
CONT_ASSIGN	191	1	0	0.00
CONT_ASSIGN	192	1	0	0.00
CONT_ASSIGN	193	1	0	0.00
CONT_ASSIGN	195	1	0	0.00
CONT_ASSIGN	201	1	0	0.00
ALWAYS	204	4	0	0.00
CONT_ASSIGN	211	1	0	0.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	218	1	0	0.00
CONT_ASSIGN	219	1	0	0.00
CONT_ASSIGN	222	1	0	0.00
CONT_ASSIGN	224	1	0	0.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	245	1	0	0.00
CONT_ASSIGN	247	1	0	0.00
CONT_ASSIGN	248	1	0	0.00
CONT_ASSIGN	251	1	0	0.00
CONT_ASSIGN	252	1	0	0.00
CONT_ASSIGN	254	1	0	0.00
CONT_ASSIGN	256	1	0	0.00
CONT_ASSIGN	260	1	0	0.00
ALWAYS	270	4	0	0.00
CONT_ASSIGN	291	1	0	0.00
CONT_ASSIGN	297	1	0	0.00
CONT_ASSIGN	299	1	0	0.00
CONT_ASSIGN	301	1	0	0.00
CONT_ASSIGN	304	1	0	0.00
CONT_ASSIGN	321	1	0	0.00
ALWAYS	324	9	0	0.00
ROUTINE	347	7	0	0.00
ROUTINE	368	9	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
121	0	1
123	0	1
126	0	1
127	0	1
128	0	1
129	0	1
130	0	1
131	0	1
			==> MISSING_ELSE
135	0	1
136	0	1
138	0	1
149	0	1
150	0	1
151	0	1
153	0	1
163	0	1
165	0	1
168	0	1
169	0	1
170	0	1
171	0	1
172	0	1
173	0	1
			==> MISSING_ELSE
177	0	1
178	0	1
180	0	1
191	0	1
192	0	1
193	0	1
195	0	1
201	0	1
204	0	1
205	0	1
206	0	1
207	0	1
			==> MISSING_ELSE
211	0	1
217	0	1
218	0	1
219	0	1
222	0	1
224	0	1
225	0	1
245	0	1
247	0	1
248	0	1
251	0	1
252	0	1
254	0	1
256	0	1
260	0	1
270	0	1
279	0	1
282	0	1
287	0	1
291	0	1
297	0	1
299	0	1
301	0	1
304	0	1
321	0	1
324	0	1
325	0	1
326	0	1
327	0	1
328	0	1
329	0	1
330	0	1
332	0	1
333	0	1
			==> MISSING_ELSE
347	0	1
349	0	1
352	0	1
353	0	1
356	0	1
357	0	1
360	0	1
368	0	1
369	0	1
370	0	1
372	0	1
373	0	1
374	0	1
376	0	1
377	0	1
379	0	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_addrfifo

	Total	Covered	Percent
Conditions	68	0	0.00
Logical	68	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       121
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       153
 EXPRESSION ((w_wptr_p == w_rptr_p) ? (5'((w_wptr_v - w_rptr_v))) : (5'(({1'b1, w_wptr_v} - {1'b0, w_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       153
 SUB-EXPRESSION (w_wptr_p == w_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       195
 EXPRESSION ((r_wptr_p == r_rptr_p) ? (5'((r_wptr_v - r_rptr_v))) : (5'(({1'b1, r_wptr_v} - {1'b0, r_rptr_v}))))
             -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       195
 SUB-EXPRESSION (r_wptr_p == r_rptr_p)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       211
 EXPRESSION (r_wptr == r_sram_rptr)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       217
 EXPRESSION (w_wptr_q == (w_rptr ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       218
 EXPRESSION (r_wptr == (r_rptr_q ^ XorMask))
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       219
 EXPRESSION (r_wptr == r_rptr_q)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       247
 EXPRESSION (r_sram_req_o && r_sram_gnt_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       248
 EXPRESSION (rvalid_o && rready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       251
 EXPRESSION (wvalid_i && ((!w_full)))
             ----1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       252
 EXPRESSION (((!w_full)) && w_sram_gnt_i)
             -----1-----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       282
 EXPRESSION (((!r_sramrptr_empty)) && rfifo_ack)
             ----------1----------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       287
 EXPRESSION (((!r_sramrptr_empty)) && ( ! (r_sram_rvalid_i ^ rfifo_ack) ))
             ----------1----------    -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       287
 SUB-EXPRESSION ( ! (r_sram_rvalid_i ^ rfifo_ack) )
                    --------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       287
 SUB-EXPRESSION (r_sram_rvalid_i ^ rfifo_ack)
                 -------1-------   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       291
 EXPRESSION (stored || r_sram_rvalid_i)
             ---1--    -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       299
 EXPRESSION (r_sram_rvalid_i ? r_sram_rdata_i[0+:Width] : (32'(0)))
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       301
 EXPRESSION (stored ? rdata_q : rdata_d)
             ---1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       321
 EXPRESSION (r_sram_rvalid_i && ( ! (stored ^ rfifo_ack) ))
             -------1-------    -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       321
 SUB-EXPRESSION ( ! (stored ^ rfifo_ack) )
                    ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       321
 SUB-EXPRESSION (stored ^ rfifo_ack)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       330
 EXPRESSION (((!r_sram_rvalid_i)) && rfifo_ack)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       349
 EXPRESSION (decval[(PtrW - 1)] ? decval_sub : decval)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       370
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo

	Line No.	Total	Covered	Percent
Branches		27	0	0.00
TERNARY	153	2	0	0.00
TERNARY	195	2	0	0.00
TERNARY	299	2	0	0.00
TERNARY	301	2	0	0.00
IF	126	3	0	0.00
IF	168	3	0	0.00
IF	204	3	0	0.00
IF	279	2	0	0.00
IF	324	4	0	0.00
TERNARY	349	2	0	0.00
IF	373	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async_sram_adapter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	153	((w_wptr_p == w_rptr_p)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	195	((r_wptr_p == r_rptr_p)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	299	(r_sram_rvalid_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	301	(stored) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	126	if ((!rst_wr_ni))
-2-:	129	if (w_wptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	168	if ((!rst_rd_ni))
-2-:	171	if (r_rptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	204	if ((!rst_rd_ni))
-2-:	206	if (r_sram_rptr_inc)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	279	if (stored)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	324	if ((!rst_rd_ni))
-2-:	327	if (store_en)
-3-:	330	if (((!r_sram_rvalid_i) && rfifo_ack))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	349	(decval[(PtrW - 1)]) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	373	if (grayval[(PtrW - 1)])

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered