Line Coverage for Module :
prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 0 | 0.00 |
| CONT_ASSIGN | 55 | 0 | 0 | |
| CONT_ASSIGN | 75 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 76 | 1 | 0 | 0.00 |
| ALWAYS | 82 | 3 | 0 | 0.00 |
| CONT_ASSIGN | 89 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 90 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 92 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 94 | 1 | 0 | 0.00 |
| ALWAYS | 96 | 5 | 0 | 0.00 |
| ALWAYS | 109 | 4 | 0 | 0.00 |
| ALWAYS | 124 | 4 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 55 |
|
unreachable |
| 75 |
0 |
1 |
| 76 |
0 |
1 |
| 82 |
0 |
1 |
| 83 |
0 |
1 |
| 84 |
0 |
1 |
| 89 |
0 |
1 |
| 90 |
0 |
1 |
| 92 |
0 |
1 |
| 94 |
0 |
1 |
| 96 |
0 |
1 |
| 97 |
0 |
1 |
| 98 |
0 |
1 |
| 100 |
0 |
1 |
| 101 |
0 |
1 |
| 103 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
| 109 |
0 |
1 |
| 110 |
0 |
1 |
| 111 |
0 |
1 |
| 112 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 124 |
0 |
1 |
| 125 |
0 |
1 |
| 126 |
0 |
1 |
| 127 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
Line Coverage for Module :
prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 0 | 0.00 |
| CONT_ASSIGN | 55 | 0 | 0 | |
| CONT_ASSIGN | 75 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 76 | 1 | 0 | 0.00 |
| ALWAYS | 82 | 3 | 0 | 0.00 |
| CONT_ASSIGN | 89 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 90 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 92 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 94 | 1 | 0 | 0.00 |
| ALWAYS | 96 | 5 | 0 | 0.00 |
| ALWAYS | 109 | 4 | 0 | 0.00 |
| ALWAYS | 124 | 4 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 55 |
|
unreachable |
| 75 |
0 |
1 |
| 76 |
0 |
1 |
| 82 |
0 |
1 |
| 83 |
0 |
1 |
| 84 |
0 |
1 |
| 89 |
0 |
1 |
| 90 |
0 |
1 |
| 92 |
0 |
1 |
| 94 |
0 |
1 |
| 96 |
0 |
1 |
| 97 |
0 |
1 |
| 98 |
0 |
1 |
| 100 |
0 |
1 |
| 101 |
0 |
1 |
| 103 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
| 109 |
0 |
1 |
| 110 |
0 |
1 |
| 111 |
0 |
1 |
| 112 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 124 |
0 |
1 |
| 125 |
0 |
1 |
| 126 |
0 |
1 |
| 127 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Module :
prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 9 | 0 | 0.00 |
| Logical | 9 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 76
EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 84
EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
----------------1--------------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 90
EXPRESSION (ready_i ? gen_normal_case.winner : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Not Covered | |
LINE 98
EXPRESSION (valid_o && ready_i)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Unreachable | |
| 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (valid_o && ((!ready_i)))
---1--- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Unreachable | |
Cond Coverage for Module :
prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 9 | 0 | 0.00 |
| Logical | 9 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 76
EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 84
EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
----------------1--------------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 90
EXPRESSION (ready_i ? gen_normal_case.winner : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Not Covered | |
LINE 98
EXPRESSION (valid_o && ready_i)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Unreachable | |
| 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (valid_o && ((!ready_i)))
---1--- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Unreachable | |
Branch Coverage for Module :
prim_arbiter_ppc
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
0 |
0.00 |
| TERNARY |
76 |
2 |
0 |
0.00 |
| TERNARY |
90 |
1 |
0 |
0.00 |
| IF |
96 |
3 |
0 |
0.00 |
| IF |
126 |
2 |
0 |
0.00 |
| IF |
111 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 ((|gen_normal_case.masked_req)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 90 (ready_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 96 if ((!rst_ni))
-2-: 98 if ((valid_o && ready_i))
-3-: 101 if ((valid_o && (!ready_i)))
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Not Covered |
|
| 0 |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
Unreachable |
|
| 0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 126 if (gen_normal_case.winner[i])
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 111 if (gen_normal_case.winner[i])
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 0 | 0.00 |
| CONT_ASSIGN | 55 | 0 | 0 | |
| CONT_ASSIGN | 75 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 76 | 1 | 0 | 0.00 |
| ALWAYS | 82 | 3 | 0 | 0.00 |
| CONT_ASSIGN | 89 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 90 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 92 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 94 | 1 | 0 | 0.00 |
| ALWAYS | 96 | 5 | 0 | 0.00 |
| ALWAYS | 109 | 4 | 0 | 0.00 |
| ALWAYS | 124 | 4 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 55 |
|
unreachable |
| 75 |
0 |
1 |
| 76 |
0 |
1 |
| 82 |
0 |
1 |
| 83 |
0 |
1 |
| 84 |
0 |
1 |
| 89 |
0 |
1 |
| 90 |
0 |
1 |
| 92 |
0 |
1 |
| 94 |
0 |
1 |
| 96 |
0 |
1 |
| 97 |
0 |
1 |
| 98 |
0 |
1 |
| 100 |
0 |
1 |
| 101 |
0 |
1 |
| 103 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
| 109 |
0 |
1 |
| 110 |
0 |
1 |
| 111 |
0 |
1 |
| 112 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 124 |
0 |
1 |
| 125 |
0 |
1 |
| 126 |
0 |
1 |
| 127 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb
| Total | Covered | Percent |
|---|
| Conditions | 9 | 0 | 0.00 |
| Logical | 9 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 76
EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 84
EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
----------------1--------------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 90
EXPRESSION (ready_i ? gen_normal_case.winner : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Not Covered | |
LINE 98
EXPRESSION (valid_o && ready_i)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Unreachable | |
| 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (valid_o && ((!ready_i)))
---1--- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
0 |
0.00 |
| TERNARY |
76 |
2 |
0 |
0.00 |
| TERNARY |
90 |
1 |
0 |
0.00 |
| IF |
96 |
3 |
0 |
0.00 |
| IF |
126 |
2 |
0 |
0.00 |
| IF |
111 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 ((|gen_normal_case.masked_req)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 90 (ready_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 96 if ((!rst_ni))
-2-: 98 if ((valid_o && ready_i))
-3-: 101 if ((valid_o && (!ready_i)))
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Not Covered |
|
| 0 |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
Unreachable |
|
| 0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 126 if (gen_normal_case.winner[i])
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 111 if (gen_normal_case.winner[i])
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 0 | 0.00 |
| CONT_ASSIGN | 55 | 0 | 0 | |
| CONT_ASSIGN | 75 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 76 | 1 | 0 | 0.00 |
| ALWAYS | 82 | 3 | 0 | 0.00 |
| CONT_ASSIGN | 89 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 90 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 92 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 94 | 1 | 0 | 0.00 |
| ALWAYS | 96 | 5 | 0 | 0.00 |
| ALWAYS | 109 | 4 | 0 | 0.00 |
| ALWAYS | 124 | 4 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 55 |
|
unreachable |
| 75 |
0 |
1 |
| 76 |
0 |
1 |
| 82 |
0 |
1 |
| 83 |
0 |
1 |
| 84 |
0 |
1 |
| 89 |
0 |
1 |
| 90 |
0 |
1 |
| 92 |
0 |
1 |
| 94 |
0 |
1 |
| 96 |
0 |
1 |
| 97 |
0 |
1 |
| 98 |
0 |
1 |
| 100 |
0 |
1 |
| 101 |
0 |
1 |
| 103 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
| 109 |
0 |
1 |
| 110 |
0 |
1 |
| 111 |
0 |
1 |
| 112 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 124 |
0 |
1 |
| 125 |
0 |
1 |
| 126 |
0 |
1 |
| 127 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb
| Total | Covered | Percent |
|---|
| Conditions | 9 | 0 | 0.00 |
| Logical | 9 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 76
EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 84
EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
----------------1--------------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 90
EXPRESSION (ready_i ? gen_normal_case.winner : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Not Covered | |
LINE 98
EXPRESSION (valid_o && ready_i)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Unreachable | |
| 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (valid_o && ((!ready_i)))
---1--- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
0 |
0.00 |
| TERNARY |
76 |
2 |
0 |
0.00 |
| TERNARY |
90 |
1 |
0 |
0.00 |
| IF |
96 |
3 |
0 |
0.00 |
| IF |
126 |
2 |
0 |
0.00 |
| IF |
111 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 ((|gen_normal_case.masked_req)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 90 (ready_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 96 if ((!rst_ni))
-2-: 98 if ((valid_o && ready_i))
-3-: 101 if ((valid_o && (!ready_i)))
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Not Covered |
|
| 0 |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
Unreachable |
|
| 0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 126 if (gen_normal_case.winner[i])
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 111 if (gen_normal_case.winner[i])
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 22 | 0 | 0.00 |
| CONT_ASSIGN | 55 | 0 | 0 | |
| CONT_ASSIGN | 75 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 76 | 1 | 0 | 0.00 |
| ALWAYS | 82 | 3 | 0 | 0.00 |
| CONT_ASSIGN | 89 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 90 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 92 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 94 | 1 | 0 | 0.00 |
| ALWAYS | 96 | 5 | 0 | 0.00 |
| ALWAYS | 109 | 4 | 0 | 0.00 |
| ALWAYS | 124 | 4 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 55 |
|
unreachable |
| 75 |
0 |
1 |
| 76 |
0 |
1 |
| 82 |
0 |
1 |
| 83 |
0 |
1 |
| 84 |
0 |
1 |
| 89 |
0 |
1 |
| 90 |
0 |
1 |
| 92 |
0 |
1 |
| 94 |
0 |
1 |
| 96 |
0 |
1 |
| 97 |
0 |
1 |
| 98 |
0 |
1 |
| 100 |
0 |
1 |
| 101 |
0 |
1 |
| 103 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
| 109 |
0 |
1 |
| 110 |
0 |
1 |
| 111 |
0 |
1 |
| 112 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
| 124 |
0 |
1 |
| 125 |
0 |
1 |
| 126 |
0 |
1 |
| 127 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb
| Total | Covered | Percent |
|---|
| Conditions | 9 | 0 | 0.00 |
| Logical | 9 | 0 | 0.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 76
EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Not Covered | |
| 1 | Not Covered | |
LINE 84
EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
----------------1--------------- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Not Covered | |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 90
EXPRESSION (ready_i ? gen_normal_case.winner : '0)
---1---
| -1- | Status | Tests |
|---|
| 0 | Unreachable | |
| 1 | Not Covered | |
LINE 98
EXPRESSION (valid_o && ready_i)
---1--- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Unreachable | |
| 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (valid_o && ((!ready_i)))
---1--- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb
| Line No. | Total | Covered | Percent |
| Branches |
|
10 |
0 |
0.00 |
| TERNARY |
76 |
2 |
0 |
0.00 |
| TERNARY |
90 |
1 |
0 |
0.00 |
| IF |
96 |
3 |
0 |
0.00 |
| IF |
126 |
2 |
0 |
0.00 |
| IF |
111 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 ((|gen_normal_case.masked_req)) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 90 (ready_i) ?
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Unreachable |
|
LineNo. Expression
-1-: 96 if ((!rst_ni))
-2-: 98 if ((valid_o && ready_i))
-3-: 101 if ((valid_o && (!ready_i)))
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Not Covered |
|
| 0 |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
Unreachable |
|
| 0 |
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 126 if (gen_normal_case.winner[i])
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|
LineNo. Expression
-1-: 111 if (gen_normal_case.winner[i])
Branches:
| -1- | Status | Tests |
| 1 |
Not Covered |
|
| 0 |
Not Covered |
|