Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
7991 |
0 |
0 |
T2 |
4695 |
316 |
0 |
0 |
T3 |
791 |
0 |
0 |
0 |
T4 |
2641 |
0 |
0 |
0 |
T5 |
4648 |
0 |
0 |
0 |
T6 |
0 |
6 |
0 |
0 |
T7 |
67456 |
0 |
0 |
0 |
T8 |
3896 |
0 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T14 |
4945 |
0 |
0 |
0 |
T15 |
4874 |
0 |
0 |
0 |
T17 |
0 |
3 |
0 |
0 |
T19 |
0 |
4 |
0 |
0 |
T20 |
0 |
3 |
0 |
0 |
T21 |
0 |
455 |
0 |
0 |
T22 |
0 |
3 |
0 |
0 |
T47 |
0 |
3 |
0 |
0 |
T52 |
0 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1083 |
0 |
0 |
T4 |
2641 |
3 |
0 |
0 |
T5 |
4648 |
3 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
2 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
107 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T35 |
0 |
121 |
0 |
0 |
T43 |
0 |
133 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
267 |
0 |
0 |
T54 |
0 |
12 |
0 |
0 |
T55 |
0 |
62 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1140 |
0 |
0 |
T4 |
2641 |
1 |
0 |
0 |
T5 |
4648 |
13 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
51 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
122 |
0 |
0 |
T29 |
0 |
3 |
0 |
0 |
T35 |
0 |
137 |
0 |
0 |
T43 |
0 |
154 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
219 |
0 |
0 |
T54 |
0 |
5 |
0 |
0 |
T55 |
0 |
29 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
5253 |
0 |
0 |
T4 |
2641 |
7 |
0 |
0 |
T5 |
4648 |
7 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
56 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
2016 |
0 |
0 |
T29 |
0 |
2 |
0 |
0 |
T35 |
0 |
161 |
0 |
0 |
T43 |
0 |
134 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
205 |
0 |
0 |
T54 |
0 |
5 |
0 |
0 |
T55 |
0 |
57 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
4601 |
0 |
0 |
T4 |
2641 |
9 |
0 |
0 |
T5 |
4648 |
11 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
28 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
1761 |
0 |
0 |
T29 |
0 |
13 |
0 |
0 |
T35 |
0 |
171 |
0 |
0 |
T43 |
0 |
137 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
221 |
0 |
0 |
T54 |
0 |
4 |
0 |
0 |
T55 |
0 |
33 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
4462 |
0 |
0 |
T4 |
2641 |
2 |
0 |
0 |
T5 |
4648 |
16 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
33 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
1673 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T35 |
0 |
144 |
0 |
0 |
T43 |
0 |
137 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
271 |
0 |
0 |
T54 |
0 |
6 |
0 |
0 |
T55 |
0 |
82 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
4026 |
0 |
0 |
T5 |
4648 |
6 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T9 |
3166 |
0 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
1243 |
0 |
0 |
T29 |
0 |
3 |
0 |
0 |
T35 |
0 |
199 |
0 |
0 |
T43 |
0 |
131 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T49 |
0 |
5 |
0 |
0 |
T53 |
0 |
229 |
0 |
0 |
T54 |
0 |
9 |
0 |
0 |
T55 |
0 |
71 |
0 |
0 |
T56 |
1205 |
0 |
0 |
0 |
T57 |
1288 |
0 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
4574 |
0 |
0 |
T4 |
2641 |
7 |
0 |
0 |
T5 |
4648 |
3 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
1932 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T35 |
0 |
146 |
0 |
0 |
T43 |
0 |
137 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
224 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
61 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
4328 |
0 |
0 |
T4 |
2641 |
1 |
0 |
0 |
T5 |
4648 |
15 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
24 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
1439 |
0 |
0 |
T29 |
0 |
2 |
0 |
0 |
T35 |
0 |
133 |
0 |
0 |
T43 |
0 |
151 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
218 |
0 |
0 |
T54 |
0 |
3 |
0 |
0 |
T55 |
0 |
37 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
5819 |
0 |
0 |
T4 |
2641 |
2 |
0 |
0 |
T5 |
4648 |
4 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
2629 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T35 |
0 |
160 |
0 |
0 |
T43 |
0 |
132 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
200 |
0 |
0 |
T54 |
0 |
10 |
0 |
0 |
T55 |
0 |
77 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
4608 |
0 |
0 |
T4 |
2641 |
5 |
0 |
0 |
T5 |
4648 |
9 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
2402 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T35 |
0 |
145 |
0 |
0 |
T43 |
0 |
103 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
215 |
0 |
0 |
T54 |
0 |
11 |
0 |
0 |
T55 |
0 |
50 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2681 |
0 |
0 |
T4 |
2641 |
9 |
0 |
0 |
T5 |
4648 |
4 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
30 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
775 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T35 |
0 |
170 |
0 |
0 |
T43 |
0 |
114 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
210 |
0 |
0 |
T54 |
0 |
7 |
0 |
0 |
T55 |
0 |
86 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2356 |
0 |
0 |
T4 |
2641 |
2 |
0 |
0 |
T5 |
4648 |
10 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
49 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
692 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T35 |
0 |
135 |
0 |
0 |
T43 |
0 |
149 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
235 |
0 |
0 |
T54 |
0 |
15 |
0 |
0 |
T55 |
0 |
58 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2221 |
0 |
0 |
T4 |
2641 |
3 |
0 |
0 |
T5 |
4648 |
11 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
63 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
782 |
0 |
0 |
T29 |
0 |
24 |
0 |
0 |
T35 |
0 |
147 |
0 |
0 |
T43 |
0 |
149 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
250 |
0 |
0 |
T54 |
0 |
11 |
0 |
0 |
T55 |
0 |
35 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2551 |
0 |
0 |
T4 |
2641 |
2 |
0 |
0 |
T5 |
4648 |
13 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
20 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
852 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T35 |
0 |
127 |
0 |
0 |
T43 |
0 |
98 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
218 |
0 |
0 |
T54 |
0 |
13 |
0 |
0 |
T55 |
0 |
59 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2299 |
0 |
0 |
T4 |
2641 |
1 |
0 |
0 |
T5 |
4648 |
16 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
18 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
609 |
0 |
0 |
T35 |
0 |
136 |
0 |
0 |
T43 |
0 |
118 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T49 |
0 |
7 |
0 |
0 |
T53 |
0 |
215 |
0 |
0 |
T55 |
0 |
7 |
0 |
0 |
T58 |
0 |
7 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2347 |
0 |
0 |
T4 |
2641 |
1 |
0 |
0 |
T5 |
4648 |
16 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
42 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
713 |
0 |
0 |
T29 |
0 |
3 |
0 |
0 |
T35 |
0 |
152 |
0 |
0 |
T43 |
0 |
135 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
175 |
0 |
0 |
T54 |
0 |
8 |
0 |
0 |
T55 |
0 |
35 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2557 |
0 |
0 |
T4 |
2641 |
4 |
0 |
0 |
T5 |
4648 |
11 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
25 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
826 |
0 |
0 |
T29 |
0 |
8 |
0 |
0 |
T35 |
0 |
133 |
0 |
0 |
T43 |
0 |
140 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
251 |
0 |
0 |
T54 |
0 |
6 |
0 |
0 |
T55 |
0 |
110 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2430 |
0 |
0 |
T4 |
2641 |
3 |
0 |
0 |
T5 |
4648 |
15 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
46 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
837 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T35 |
0 |
192 |
0 |
0 |
T43 |
0 |
130 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
172 |
0 |
0 |
T54 |
0 |
9 |
0 |
0 |
T55 |
0 |
38 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2458 |
0 |
0 |
T4 |
2641 |
7 |
0 |
0 |
T5 |
4648 |
12 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
672 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T35 |
0 |
147 |
0 |
0 |
T43 |
0 |
144 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
212 |
0 |
0 |
T54 |
0 |
4 |
0 |
0 |
T55 |
0 |
52 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2358 |
0 |
0 |
T4 |
2641 |
7 |
0 |
0 |
T5 |
4648 |
9 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
14 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
706 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T35 |
0 |
144 |
0 |
0 |
T43 |
0 |
99 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
233 |
0 |
0 |
T54 |
0 |
8 |
0 |
0 |
T55 |
0 |
76 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2236 |
0 |
0 |
T4 |
2641 |
3 |
0 |
0 |
T5 |
4648 |
11 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
23 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
785 |
0 |
0 |
T29 |
0 |
6 |
0 |
0 |
T35 |
0 |
127 |
0 |
0 |
T43 |
0 |
110 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
225 |
0 |
0 |
T54 |
0 |
7 |
0 |
0 |
T55 |
0 |
73 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2366 |
0 |
0 |
T4 |
2641 |
3 |
0 |
0 |
T5 |
4648 |
15 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
50 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
544 |
0 |
0 |
T35 |
0 |
197 |
0 |
0 |
T43 |
0 |
133 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T49 |
0 |
8 |
0 |
0 |
T53 |
0 |
234 |
0 |
0 |
T54 |
0 |
15 |
0 |
0 |
T55 |
0 |
57 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2740 |
0 |
0 |
T4 |
2641 |
8 |
0 |
0 |
T5 |
4648 |
15 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
46 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
665 |
0 |
0 |
T29 |
0 |
14 |
0 |
0 |
T35 |
0 |
164 |
0 |
0 |
T43 |
0 |
137 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
233 |
0 |
0 |
T54 |
0 |
9 |
0 |
0 |
T55 |
0 |
122 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2663 |
0 |
0 |
T4 |
2641 |
3 |
0 |
0 |
T5 |
4648 |
18 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
30 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
856 |
0 |
0 |
T35 |
0 |
126 |
0 |
0 |
T43 |
0 |
97 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T49 |
0 |
1 |
0 |
0 |
T53 |
0 |
203 |
0 |
0 |
T54 |
0 |
9 |
0 |
0 |
T55 |
0 |
49 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2469 |
0 |
0 |
T4 |
2641 |
3 |
0 |
0 |
T5 |
4648 |
12 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
24 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
730 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T35 |
0 |
174 |
0 |
0 |
T43 |
0 |
129 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
228 |
0 |
0 |
T54 |
0 |
5 |
0 |
0 |
T55 |
0 |
80 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2559 |
0 |
0 |
T4 |
2641 |
2 |
0 |
0 |
T5 |
4648 |
9 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
51 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
722 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T35 |
0 |
165 |
0 |
0 |
T43 |
0 |
133 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
232 |
0 |
0 |
T54 |
0 |
3 |
0 |
0 |
T55 |
0 |
43 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2238 |
0 |
0 |
T4 |
2641 |
4 |
0 |
0 |
T5 |
4648 |
3 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
45 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
615 |
0 |
0 |
T29 |
0 |
16 |
0 |
0 |
T35 |
0 |
175 |
0 |
0 |
T43 |
0 |
177 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
218 |
0 |
0 |
T54 |
0 |
5 |
0 |
0 |
T55 |
0 |
106 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2369 |
0 |
0 |
T4 |
2641 |
2 |
0 |
0 |
T5 |
4648 |
9 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
10 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
713 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T35 |
0 |
148 |
0 |
0 |
T43 |
0 |
141 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
267 |
0 |
0 |
T54 |
0 |
15 |
0 |
0 |
T55 |
0 |
26 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2417 |
0 |
0 |
T4 |
2641 |
4 |
0 |
0 |
T5 |
4648 |
14 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
48 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
679 |
0 |
0 |
T35 |
0 |
162 |
0 |
0 |
T43 |
0 |
144 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T49 |
0 |
6 |
0 |
0 |
T53 |
0 |
186 |
0 |
0 |
T54 |
0 |
7 |
0 |
0 |
T55 |
0 |
54 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2485 |
0 |
0 |
T4 |
2641 |
3 |
0 |
0 |
T5 |
4648 |
8 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
904 |
0 |
0 |
T35 |
0 |
128 |
0 |
0 |
T43 |
0 |
140 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T49 |
0 |
6 |
0 |
0 |
T53 |
0 |
210 |
0 |
0 |
T54 |
0 |
8 |
0 |
0 |
T55 |
0 |
24 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2643 |
0 |
0 |
T4 |
2641 |
1 |
0 |
0 |
T5 |
4648 |
4 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
751 |
0 |
0 |
T29 |
0 |
13 |
0 |
0 |
T35 |
0 |
122 |
0 |
0 |
T43 |
0 |
112 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
251 |
0 |
0 |
T54 |
0 |
11 |
0 |
0 |
T55 |
0 |
117 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2280 |
0 |
0 |
T4 |
2641 |
7 |
0 |
0 |
T5 |
4648 |
9 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
32 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
649 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T35 |
0 |
149 |
0 |
0 |
T43 |
0 |
129 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
219 |
0 |
0 |
T54 |
0 |
7 |
0 |
0 |
T55 |
0 |
45 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2403 |
0 |
0 |
T4 |
2641 |
5 |
0 |
0 |
T5 |
4648 |
7 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
22 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
708 |
0 |
0 |
T29 |
0 |
2 |
0 |
0 |
T35 |
0 |
169 |
0 |
0 |
T43 |
0 |
145 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
236 |
0 |
0 |
T54 |
0 |
14 |
0 |
0 |
T55 |
0 |
55 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2355 |
0 |
0 |
T4 |
2641 |
2 |
0 |
0 |
T5 |
4648 |
17 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
28 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
817 |
0 |
0 |
T29 |
0 |
14 |
0 |
0 |
T35 |
0 |
162 |
0 |
0 |
T43 |
0 |
157 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
221 |
0 |
0 |
T54 |
0 |
1 |
0 |
0 |
T55 |
0 |
26 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1164 |
0 |
0 |
T4 |
2641 |
7 |
0 |
0 |
T5 |
4648 |
13 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
35 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
179 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T35 |
0 |
138 |
0 |
0 |
T43 |
0 |
137 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
182 |
0 |
0 |
T54 |
0 |
7 |
0 |
0 |
T55 |
0 |
80 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1161 |
0 |
0 |
T4 |
2641 |
5 |
0 |
0 |
T5 |
4648 |
10 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
57 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
198 |
0 |
0 |
T35 |
0 |
184 |
0 |
0 |
T43 |
0 |
130 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
196 |
0 |
0 |
T54 |
0 |
11 |
0 |
0 |
T55 |
0 |
43 |
0 |
0 |
T58 |
0 |
8 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1215 |
0 |
0 |
T4 |
2641 |
6 |
0 |
0 |
T5 |
4648 |
16 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
8 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
170 |
0 |
0 |
T29 |
0 |
3 |
0 |
0 |
T35 |
0 |
169 |
0 |
0 |
T43 |
0 |
164 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
247 |
0 |
0 |
T54 |
0 |
16 |
0 |
0 |
T55 |
0 |
36 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1226 |
0 |
0 |
T4 |
2641 |
7 |
0 |
0 |
T5 |
4648 |
9 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
63 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
201 |
0 |
0 |
T35 |
0 |
166 |
0 |
0 |
T43 |
0 |
140 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T49 |
0 |
2 |
0 |
0 |
T53 |
0 |
283 |
0 |
0 |
T54 |
0 |
3 |
0 |
0 |
T55 |
0 |
56 |
0 |
0 |
control_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1568 |
0 |
0 |
T4 |
2641 |
7 |
0 |
0 |
T5 |
4648 |
14 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
29 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
318 |
0 |
0 |
T29 |
0 |
1 |
0 |
0 |
T35 |
0 |
174 |
0 |
0 |
T43 |
0 |
168 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
230 |
0 |
0 |
T54 |
0 |
7 |
0 |
0 |
T55 |
0 |
96 |
0 |
0 |
fifo_level_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1239 |
0 |
0 |
T4 |
2641 |
5 |
0 |
0 |
T5 |
4648 |
12 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
54 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
172 |
0 |
0 |
T29 |
0 |
13 |
0 |
0 |
T35 |
0 |
119 |
0 |
0 |
T43 |
0 |
144 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
236 |
0 |
0 |
T54 |
0 |
3 |
0 |
0 |
T55 |
0 |
36 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1449 |
0 |
0 |
T4 |
2641 |
2 |
0 |
0 |
T5 |
4648 |
10 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
28 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
270 |
0 |
0 |
T29 |
0 |
13 |
0 |
0 |
T35 |
0 |
128 |
0 |
0 |
T43 |
0 |
173 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
218 |
0 |
0 |
T54 |
0 |
6 |
0 |
0 |
T55 |
0 |
54 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
2881 |
0 |
0 |
T4 |
2641 |
1 |
0 |
0 |
T5 |
4648 |
17 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
36 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
801 |
0 |
0 |
T35 |
0 |
159 |
0 |
0 |
T43 |
0 |
108 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
254 |
0 |
0 |
T54 |
0 |
10 |
0 |
0 |
T55 |
0 |
101 |
0 |
0 |
T59 |
0 |
19 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1314 |
0 |
0 |
T4 |
2641 |
2 |
0 |
0 |
T5 |
4648 |
8 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
38 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
173 |
0 |
0 |
T29 |
0 |
6 |
0 |
0 |
T35 |
0 |
120 |
0 |
0 |
T43 |
0 |
170 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
209 |
0 |
0 |
T54 |
0 |
10 |
0 |
0 |
T55 |
0 |
65 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1294 |
0 |
0 |
T4 |
2641 |
1 |
0 |
0 |
T5 |
4648 |
18 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
68 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
167 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T35 |
0 |
193 |
0 |
0 |
T43 |
0 |
115 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
240 |
0 |
0 |
T54 |
0 |
7 |
0 |
0 |
T55 |
0 |
84 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1106 |
0 |
0 |
T4 |
2641 |
7 |
0 |
0 |
T5 |
4648 |
13 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
31 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
115 |
0 |
0 |
T29 |
0 |
8 |
0 |
0 |
T35 |
0 |
113 |
0 |
0 |
T43 |
0 |
104 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
228 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
23 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
993 |
0 |
0 |
T4 |
2641 |
6 |
0 |
0 |
T5 |
4648 |
19 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
61 |
0 |
0 |
T29 |
0 |
1 |
0 |
0 |
T35 |
0 |
144 |
0 |
0 |
T43 |
0 |
109 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
255 |
0 |
0 |
T54 |
0 |
3 |
0 |
0 |
T55 |
0 |
71 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1135 |
0 |
0 |
T4 |
2641 |
8 |
0 |
0 |
T5 |
4648 |
8 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
100 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T35 |
0 |
191 |
0 |
0 |
T43 |
0 |
107 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
262 |
0 |
0 |
T54 |
0 |
12 |
0 |
0 |
T55 |
0 |
39 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1080 |
0 |
0 |
T5 |
4648 |
18 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T9 |
3166 |
0 |
0 |
0 |
T10 |
0 |
54 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
133 |
0 |
0 |
T29 |
0 |
3 |
0 |
0 |
T35 |
0 |
134 |
0 |
0 |
T43 |
0 |
149 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T49 |
0 |
9 |
0 |
0 |
T53 |
0 |
213 |
0 |
0 |
T54 |
0 |
6 |
0 |
0 |
T55 |
0 |
82 |
0 |
0 |
T56 |
1205 |
0 |
0 |
0 |
T57 |
1288 |
0 |
0 |
0 |
rxf_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1186 |
0 |
0 |
T4 |
2641 |
8 |
0 |
0 |
T5 |
4648 |
11 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
37 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
129 |
0 |
0 |
T29 |
0 |
14 |
0 |
0 |
T35 |
0 |
103 |
0 |
0 |
T43 |
0 |
139 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
216 |
0 |
0 |
T54 |
0 |
1 |
0 |
0 |
T55 |
0 |
77 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1582 |
0 |
0 |
T4 |
2641 |
2 |
0 |
0 |
T5 |
4648 |
12 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
93 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
246 |
0 |
0 |
T29 |
0 |
9 |
0 |
0 |
T35 |
0 |
179 |
0 |
0 |
T43 |
0 |
139 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
248 |
0 |
0 |
T54 |
0 |
8 |
0 |
0 |
T55 |
0 |
36 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1209 |
0 |
0 |
T4 |
2641 |
1 |
0 |
0 |
T5 |
4648 |
9 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
59 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
99 |
0 |
0 |
T29 |
0 |
4 |
0 |
0 |
T35 |
0 |
159 |
0 |
0 |
T43 |
0 |
140 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
250 |
0 |
0 |
T54 |
0 |
4 |
0 |
0 |
T55 |
0 |
48 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1642 |
0 |
0 |
T4 |
2641 |
5 |
0 |
0 |
T5 |
4648 |
11 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
54 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
338 |
0 |
0 |
T29 |
0 |
2 |
0 |
0 |
T35 |
0 |
147 |
0 |
0 |
T43 |
0 |
149 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
229 |
0 |
0 |
T54 |
0 |
7 |
0 |
0 |
T55 |
0 |
73 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1216 |
0 |
0 |
T4 |
2641 |
6 |
0 |
0 |
T5 |
4648 |
13 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
50 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
192 |
0 |
0 |
T29 |
0 |
2 |
0 |
0 |
T35 |
0 |
122 |
0 |
0 |
T43 |
0 |
149 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
213 |
0 |
0 |
T54 |
0 |
8 |
0 |
0 |
T55 |
0 |
75 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1130 |
0 |
0 |
T4 |
2641 |
2 |
0 |
0 |
T5 |
4648 |
4 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
17 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
101 |
0 |
0 |
T29 |
0 |
10 |
0 |
0 |
T35 |
0 |
144 |
0 |
0 |
T43 |
0 |
135 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
236 |
0 |
0 |
T54 |
0 |
7 |
0 |
0 |
T55 |
0 |
31 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
963 |
0 |
0 |
T4 |
2641 |
3 |
0 |
0 |
T5 |
4648 |
11 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
37 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
110 |
0 |
0 |
T29 |
0 |
8 |
0 |
0 |
T35 |
0 |
143 |
0 |
0 |
T43 |
0 |
148 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
176 |
0 |
0 |
T54 |
0 |
7 |
0 |
0 |
T55 |
0 |
49 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1115 |
0 |
0 |
T5 |
4648 |
16 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T9 |
3166 |
0 |
0 |
0 |
T10 |
0 |
31 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
107 |
0 |
0 |
T25 |
0 |
3 |
0 |
0 |
T29 |
0 |
7 |
0 |
0 |
T35 |
0 |
178 |
0 |
0 |
T43 |
0 |
199 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
213 |
0 |
0 |
T54 |
0 |
4 |
0 |
0 |
T55 |
0 |
47 |
0 |
0 |
T56 |
1205 |
0 |
0 |
0 |
T57 |
1288 |
0 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1249 |
0 |
0 |
T4 |
2641 |
4 |
0 |
0 |
T5 |
4648 |
22 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
61 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
118 |
0 |
0 |
T29 |
0 |
12 |
0 |
0 |
T35 |
0 |
146 |
0 |
0 |
T43 |
0 |
180 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
290 |
0 |
0 |
T54 |
0 |
2 |
0 |
0 |
T55 |
0 |
42 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
994 |
0 |
0 |
T4 |
2641 |
5 |
0 |
0 |
T5 |
4648 |
17 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T10 |
0 |
56 |
0 |
0 |
T11 |
24580 |
0 |
0 |
0 |
T12 |
997 |
0 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
130 |
0 |
0 |
T35 |
0 |
140 |
0 |
0 |
T43 |
0 |
102 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
203 |
0 |
0 |
T54 |
0 |
11 |
0 |
0 |
T55 |
0 |
56 |
0 |
0 |
T58 |
0 |
16 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1095 |
0 |
0 |
T5 |
4648 |
20 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T9 |
3166 |
0 |
0 |
0 |
T10 |
0 |
11 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
95 |
0 |
0 |
T29 |
0 |
5 |
0 |
0 |
T35 |
0 |
137 |
0 |
0 |
T43 |
0 |
142 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T49 |
0 |
3 |
0 |
0 |
T53 |
0 |
249 |
0 |
0 |
T54 |
0 |
6 |
0 |
0 |
T55 |
0 |
71 |
0 |
0 |
T56 |
1205 |
0 |
0 |
0 |
T57 |
1288 |
0 |
0 |
0 |
txf_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1958678 |
1270 |
0 |
0 |
T5 |
4648 |
16 |
0 |
0 |
T6 |
2557 |
0 |
0 |
0 |
T9 |
3166 |
0 |
0 |
0 |
T10 |
0 |
21 |
0 |
0 |
T13 |
1466 |
0 |
0 |
0 |
T16 |
4940 |
0 |
0 |
0 |
T19 |
0 |
188 |
0 |
0 |
T29 |
0 |
3 |
0 |
0 |
T35 |
0 |
158 |
0 |
0 |
T43 |
0 |
159 |
0 |
0 |
T44 |
1234 |
0 |
0 |
0 |
T45 |
1366 |
0 |
0 |
0 |
T46 |
1098 |
0 |
0 |
0 |
T53 |
0 |
205 |
0 |
0 |
T54 |
0 |
8 |
0 |
0 |
T55 |
0 |
60 |
0 |
0 |
T56 |
1205 |
0 |
0 |
0 |
T57 |
1288 |
0 |
0 |
0 |
T58 |
0 |
6 |
0 |
0 |