Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

265339

1

T1

1193

T2

1259

T3

460

full_word

245667

1

T1

267

T2

1795

T3

72

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	510566	1			T1	1460		T2	3054		T3	532
auto[TlIntgErrCmd]	143	1			T5	5		T6	5		T23	10
auto[TlIntgErrData]	145	1			T5	11		T6	11		T23	10
auto[TlIntgErrBoth]	152	1			T5	4		T6	4		T23	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

339409

1

T1

1242

T2

1383

T3

43

auto[1]

171597

1

T1

218

T2

1671

T3

489

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	229802	1			T1	1173		T2	1259		T3	23
auto[TlIntgErrNone]	partial	auto[1]	35122	1			T1	20		T3	437		T7	10
auto[TlIntgErrNone]	full_word	auto[0]	109412	1			T1	69		T2	124		T3	20
auto[TlIntgErrNone]	full_word	auto[1]	136230	1			T1	198		T2	1671		T3	52
auto[TlIntgErrCmd]	partial	auto[0]	60	1			T5	3		T6	1		T23	2
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T5	2		T6	3		T23	8
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T57	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T6	1		T24	2		T58	1
auto[TlIntgErrData]	partial	auto[0]	67	1			T5	6		T6	5		T23	4
auto[TlIntgErrData]	partial	auto[1]	71	1			T5	4		T6	6		T23	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T5	1		T23	1		T58	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T24	1		T59	1		T60	1
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T5	1		T23	4		T24	2
auto[TlIntgErrBoth]	partial	auto[1]	83	1			T5	2		T6	2		T23	6
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T25	1		T55	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T5	1		T6	2		T61	1