Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic 0.00 0.00 0.00
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic 0.00 0.00 0.00
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic 0.00 0.00 0.00
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic 0.00 0.00 0.00
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic 0.00 0.00 0.00
tb.dut.u_tx_rst_scan_mux.gen_generic.u_impl_generic 0.00 0.00 0.00
tb.dut.u_rx_rst_scan_mux.gen_generic.u_impl_generic 0.00 0.00 0.00
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic 0.00 0.00 0.00
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic 0.00 0.00 0.00
tb.dut.u_sram_clk_sel.gen_generic.u_impl_generic 0.00 0.00 0.00
tb.dut.u_sram_clk_scan.gen_generic.u_impl_generic 0.00 0.00 0.00
tb.dut.u_sram_rst_sel.gen_generic.u_impl_generic 0.00 0.00 0.00
tb.dut.u_sram_rst_scanmux.gen_generic.u_impl_generic 0.00 0.00 0.00


Module Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_spi_in_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_spi_out_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_csb_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_csb_rst_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tx_rst_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tx_rst_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_rx_rst_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rx_rst_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tpm_csb_rst_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sram_clk_sel.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sram_clk_sel


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sram_clk_scan.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sram_clk_scan


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sram_rst_sel.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sram_rst_sel


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sram_rst_scanmux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sram_rst_scanmux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_tx_rst_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_tx_rst_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_rx_rst_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_rx_rst_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_sram_clk_sel.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_sram_clk_sel.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_sram_clk_scan.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_sram_clk_scan.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_sram_rst_sel.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_sram_rst_sel.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Line Coverage for Instance : tb.dut.u_sram_rst_scanmux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL100.00
CONT_ASSIGN17100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 0 1

Cond Coverage for Instance : tb.dut.u_sram_rst_scanmux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%