Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_intr_hw
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_intr_rxf 0.00 0.00 0.00 0.00
tb.dut.u_intr_rxlvl 0.00 0.00 0.00 0.00
tb.dut.u_intr_txlvl 0.00 0.00 0.00 0.00
tb.dut.u_intr_rxerr 0.00 0.00 0.00 0.00
tb.dut.u_intr_rxoverflow 0.00 0.00 0.00 0.00
tb.dut.u_intr_txunderflow 0.00 0.00 0.00 0.00
tb.dut.u_intr_cmdfifo_not_empty 0.00 0.00 0.00 0.00
tb.dut.u_intr_payload_not_empty 0.00 0.00 0.00 0.00
tb.dut.u_intr_payload_overflow 0.00 0.00 0.00 0.00
tb.dut.u_intr_readbuf_watermark 0.00 0.00 0.00 0.00
tb.dut.u_intr_readbuf_flip 0.00 0.00 0.00 0.00
tb.dut.u_intr_tpm_cmdaddr_notempty 0.00 0.00 0.00 0.00


Module Instance : tb.dut.u_intr_rxf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_intr_rxlvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_intr_txlvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_intr_rxerr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_intr_rxoverflow

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_intr_txunderflow

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_intr_cmdfifo_not_empty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_intr_payload_not_empty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_intr_payload_overflow

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_intr_readbuf_watermark

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_intr_readbuf_flip

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_intr_tpm_cmdaddr_notempty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
19.21 0.00 0.00 76.82 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.u_intr_rxf

SCORELINE
0.00 0.00
tb.dut.u_intr_rxlvl

SCORELINE
0.00 0.00
tb.dut.u_intr_txlvl

SCORELINE
0.00 0.00
tb.dut.u_intr_rxerr

SCORELINE
0.00 0.00
tb.dut.u_intr_rxoverflow

SCORELINE
0.00 0.00
tb.dut.u_intr_txunderflow

SCORELINE
0.00 0.00
tb.dut.u_intr_cmdfifo_not_empty

SCORELINE
0.00 0.00
tb.dut.u_intr_payload_not_empty

SCORELINE
0.00 0.00
tb.dut.u_intr_payload_overflow

SCORELINE
0.00 0.00
tb.dut.u_intr_readbuf_watermark

SCORELINE
0.00 0.00
tb.dut.u_intr_readbuf_flip

Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.u_intr_tpm_cmdaddr_notempty

Line No.TotalCoveredPercent
TOTAL1000.00
ALWAYS60400.00
CONT_ASSIGN66100.00
CONT_ASSIGN68100.00
CONT_ASSIGN73100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 0 2
61 0 2
==> MISSING_ELSE
66 0 1
68 0 1
73 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.u_intr_rxf

SCORECOND
0.00 0.00
tb.dut.u_intr_rxlvl

SCORECOND
0.00 0.00
tb.dut.u_intr_txlvl

SCORECOND
0.00 0.00
tb.dut.u_intr_rxerr

SCORECOND
0.00 0.00
tb.dut.u_intr_rxoverflow

SCORECOND
0.00 0.00
tb.dut.u_intr_txunderflow

SCORECOND
0.00 0.00
tb.dut.u_intr_cmdfifo_not_empty

SCORECOND
0.00 0.00
tb.dut.u_intr_payload_not_empty

SCORECOND
0.00 0.00
tb.dut.u_intr_payload_overflow

SCORECOND
0.00 0.00
tb.dut.u_intr_readbuf_watermark

SCORECOND
0.00 0.00
tb.dut.u_intr_readbuf_flip

TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.u_intr_tpm_cmdaddr_notempty

TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       68
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :
SCOREBRANCH
0.00 0.00
tb.dut.u_intr_rxf

SCOREBRANCH
0.00 0.00
tb.dut.u_intr_rxlvl

SCOREBRANCH
0.00 0.00
tb.dut.u_intr_txlvl

SCOREBRANCH
0.00 0.00
tb.dut.u_intr_rxerr

SCOREBRANCH
0.00 0.00
tb.dut.u_intr_rxoverflow

SCOREBRANCH
0.00 0.00
tb.dut.u_intr_txunderflow

SCOREBRANCH
0.00 0.00
tb.dut.u_intr_cmdfifo_not_empty

SCOREBRANCH
0.00 0.00
tb.dut.u_intr_payload_not_empty

SCOREBRANCH
0.00 0.00
tb.dut.u_intr_payload_overflow

SCOREBRANCH
0.00 0.00
tb.dut.u_intr_readbuf_watermark

SCOREBRANCH
0.00 0.00
tb.dut.u_intr_readbuf_flip

Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :
SCOREBRANCH
0.00 0.00
tb.dut.u_intr_tpm_cmdaddr_notempty

Line No.TotalCoveredPercent
Branches 5 0 0.00
IF 60 3 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	60	if ((!rst_ni))
-2-:	61	if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_intr_rxf
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.u_intr_rxf
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.u_intr_rxf
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_intr_rxlvl
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.u_intr_rxlvl
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.u_intr_rxlvl
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_intr_txlvl
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.u_intr_txlvl
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.u_intr_txlvl
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_intr_rxerr
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.u_intr_rxerr
TotalCoveredPercent
Conditions1100.00
Logical1100.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Unreachable
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.u_intr_rxerr
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_intr_rxoverflow
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.u_intr_rxoverflow
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.u_intr_rxoverflow
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_intr_txunderflow
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.u_intr_txunderflow
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.u_intr_txunderflow
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_intr_cmdfifo_not_empty
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.u_intr_cmdfifo_not_empty
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.u_intr_cmdfifo_not_empty
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_intr_payload_not_empty
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.u_intr_payload_not_empty
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.u_intr_payload_not_empty
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_intr_payload_overflow
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.u_intr_payload_overflow
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.u_intr_payload_overflow
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_intr_readbuf_watermark
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.u_intr_readbuf_watermark
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.u_intr_readbuf_watermark
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_intr_readbuf_flip
Line No.TotalCoveredPercent
TOTAL700.00
CONT_ASSIGN47100.00
CONT_ASSIGN49100.00
CONT_ASSIGN52100.00
CONT_ASSIGN54100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
47 0 1
49 0 1
52 0 1
54 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.u_intr_readbuf_flip
TotalCoveredPercent
Conditions1200.00
Logical1200.00
Non-Logical00
Event00

 LINE       47
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       47
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       52
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.u_intr_readbuf_flip
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_intr_tpm_cmdaddr_notempty
Line No.TotalCoveredPercent
TOTAL1000.00
ALWAYS60400.00
CONT_ASSIGN66100.00
CONT_ASSIGN68100.00
CONT_ASSIGN73100.00
ALWAYS80300.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 0 2
61 0 2
==> MISSING_ELSE
66 0 1
68 0 1
73 0 1
80 0 1
81 0 1
83 0 1

Cond Coverage for Instance : tb.dut.u_intr_tpm_cmdaddr_notempty
TotalCoveredPercent
Conditions900.00
Logical900.00
Non-Logical00
Event00

 LINE       66
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       68
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       83
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Instance : tb.dut.u_intr_tpm_cmdaddr_notempty
Line No.TotalCoveredPercent
Branches 5 0 0.00
IF 60 3 0 0.00
IF 80 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	60	if ((!rst_ni))
-2-:	61	if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	80	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%