Unified Coverage Report :: Module :: prim_rst_sync

Module : prim_rst_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tpm_csb_rst_sync	0.00	0.00

---

Module Instance : tb.dut.u_tpm_csb_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
19.21	0.00	0.00	76.82		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	0.00	0.00	0.00
u_sync	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	35	1	0	0.00
CONT_ASSIGN	36	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	0	1
36	0	1