Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	162262497	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

19021178

1

T4

262

T5

8

T6

107

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	169161663	1			T4	544		T5	1		T6	3406
values[0x0]	6056645	1			T4	66		T5	13		T6	35
values[0x1]	6065367	1			T4	50		T5	10		T6	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	82719569	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

98564106

1

T4

391

T5

10

T6

1218

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	672602	1			T4	2		T6	16		T7	4
valid_sources[0x01]	703546	1			T4	3		T6	21		T12	5
valid_sources[0x02]	675298	1			T4	3		T6	11		T12	4
valid_sources[0x03]	705864	1			T4	1		T6	5		T7	5
valid_sources[0x04]	694173	1			T4	9		T6	17		T7	4
valid_sources[0x05]	727147	1			T4	1		T6	8		T7	3
valid_sources[0x06]	727952	1			T6	7		T7	9		T12	2
valid_sources[0x07]	681078	1			T4	2		T6	20		T7	11
valid_sources[0x08]	724312	1			T4	3		T6	17		T12	1
valid_sources[0x09]	662221	1			T4	3		T6	16		T7	15
valid_sources[0x0a]	705636	1			T4	4		T6	10		T12	6
valid_sources[0x0b]	741501	1			T4	1		T6	4		T7	8
valid_sources[0x0c]	708832	1			T6	7		T7	4		T12	7
valid_sources[0x0d]	709698	1			T4	1		T6	4		T7	2
valid_sources[0x0e]	697413	1			T4	4		T6	17		T7	5
valid_sources[0x0f]	678085	1			T4	3		T6	4		T12	4
valid_sources[0x10]	690967	1			T4	6		T6	13		T7	4
valid_sources[0x11]	678826	1			T4	1		T6	22		T7	5
valid_sources[0x12]	693850	1			T4	1		T6	23		T12	1
valid_sources[0x13]	697654	1			T4	10		T6	19		T7	1
valid_sources[0x14]	680901	1			T4	7		T6	9		T12	6
valid_sources[0x15]	687010	1			T4	1		T6	16		T12	5
valid_sources[0x16]	688656	1			T4	9		T6	30		T12	1
valid_sources[0x17]	680187	1			T4	1		T6	8		T7	3
valid_sources[0x18]	698988	1			T4	2		T6	12		T7	14
valid_sources[0x19]	713980	1			T4	3		T6	8		T7	1
valid_sources[0x1a]	683856	1			T4	3		T6	18		T1	244
valid_sources[0x1b]	717458	1			T4	1		T6	26		T12	2
valid_sources[0x1c]	676712	1			T4	1		T6	11		T7	10
valid_sources[0x1d]	695563	1			T4	4		T6	10		T12	6
valid_sources[0x1e]	711299	1			T4	2		T6	18		T7	2
valid_sources[0x1f]	758140	1			T4	7		T6	10		T12	2
valid_sources[0x20]	734987	1			T4	8		T6	18		T7	6
valid_sources[0x21]	692690	1			T4	1		T6	6		T7	5
valid_sources[0x22]	740627	1			T4	1		T6	3		T12	1
valid_sources[0x23]	681494	1			T4	1		T6	10		T12	2
valid_sources[0x24]	684083	1			T4	3		T6	3		T7	6
valid_sources[0x25]	710126	1			T4	2		T6	16		T12	4
valid_sources[0x26]	689477	1			T4	2		T6	3		T12	8
valid_sources[0x27]	677782	1			T4	1		T6	16		T7	11
valid_sources[0x28]	729561	1			T6	9		T12	2		T1	275
valid_sources[0x29]	1312832	1			T6	14		T12	8		T1	271
valid_sources[0x2a]	706695	1			T4	6		T6	15		T7	1
valid_sources[0x2b]	706150	1			T4	2		T6	9		T12	4
valid_sources[0x2c]	686774	1			T4	3		T6	18		T7	1
valid_sources[0x2d]	714336	1			T4	2		T6	11		T7	11
valid_sources[0x2e]	703701	1			T6	9		T7	6		T12	5
valid_sources[0x2f]	705941	1			T4	3		T6	16		T12	2
valid_sources[0x30]	704099	1			T6	29		T7	20		T12	5
valid_sources[0x31]	701320	1			T6	7		T12	9		T1	271
valid_sources[0x32]	666363	1			T4	3		T6	10		T12	8
valid_sources[0x33]	741109	1			T4	4		T6	9		T7	11
valid_sources[0x34]	716949	1			T4	4		T6	9		T7	4
valid_sources[0x35]	725119	1			T4	2		T6	30		T7	11
valid_sources[0x36]	692208	1			T4	3		T6	10		T7	10
valid_sources[0x37]	687160	1			T4	1		T6	4		T12	10
valid_sources[0x38]	702827	1			T4	9		T6	15		T7	4
valid_sources[0x39]	723862	1			T4	1		T6	15		T7	21
valid_sources[0x3a]	662480	1			T4	1		T6	5		T7	12
valid_sources[0x3b]	727948	1			T4	4		T6	8		T7	5
valid_sources[0x3c]	693776	1			T6	23		T7	2		T12	2
valid_sources[0x3d]	683242	1			T4	1		T6	4		T7	5
valid_sources[0x3e]	707828	1			T4	2		T6	9		T7	9
valid_sources[0x3f]	707262	1			T4	5		T6	11		T7	3
valid_sources[0x40]	687865	1			T6	29		T7	9		T12	9
valid_sources[0x41]	689051	1			T4	3		T6	11		T12	10
valid_sources[0x42]	698123	1			T6	6		T7	18		T12	2
valid_sources[0x43]	728506	1			T6	21		T7	5		T12	5
valid_sources[0x44]	718426	1			T4	4		T6	22		T12	8
valid_sources[0x45]	747949	1			T6	25		T12	5		T1	246
valid_sources[0x46]	704845	1			T4	5		T6	7		T7	7
valid_sources[0x47]	716619	1			T6	11		T7	14		T12	4
valid_sources[0x48]	730693	1			T6	19		T12	4		T1	256
valid_sources[0x49]	727409	1			T4	3		T6	13		T7	4
valid_sources[0x4a]	681139	1			T4	4		T6	10		T7	8
valid_sources[0x4b]	710291	1			T4	3		T6	8		T7	6
valid_sources[0x4c]	706157	1			T4	2		T6	14		T7	8
valid_sources[0x4d]	716503	1			T4	9		T6	14		T7	1
valid_sources[0x4e]	699105	1			T4	4		T6	15		T12	2
valid_sources[0x4f]	693385	1			T4	3		T6	8		T7	1
valid_sources[0x50]	686412	1			T4	5		T6	18		T12	4
valid_sources[0x51]	660857	1			T6	12		T7	14		T12	1
valid_sources[0x52]	737284	1			T4	3		T6	7		T7	15
valid_sources[0x53]	716707	1			T4	4		T6	15		T7	9
valid_sources[0x54]	737713	1			T6	9		T12	6		T1	309
valid_sources[0x55]	736738	1			T4	4		T6	20		T7	6
valid_sources[0x56]	713551	1			T4	3		T6	12		T7	4
valid_sources[0x57]	704008	1			T6	14		T7	1		T12	13
valid_sources[0x58]	652051	1			T4	2		T6	24		T7	3
valid_sources[0x59]	719733	1			T4	11		T6	10		T12	4
valid_sources[0x5a]	708234	1			T4	1		T6	6		T7	6
valid_sources[0x5b]	706782	1			T4	1		T6	10		T7	4
valid_sources[0x5c]	711164	1			T4	2		T6	8		T7	5
valid_sources[0x5d]	664505	1			T4	2		T6	18		T7	1
valid_sources[0x5e]	704479	1			T4	5		T6	21		T7	15
valid_sources[0x5f]	711310	1			T4	1		T6	9		T7	1
valid_sources[0x60]	716947	1			T4	1		T6	34		T7	6
valid_sources[0x61]	741734	1			T4	1		T6	10		T7	1
valid_sources[0x62]	692335	1			T4	3		T6	11		T7	5
valid_sources[0x63]	674845	1			T4	3		T6	18		T7	7
valid_sources[0x64]	689989	1			T4	4		T6	8		T12	5
valid_sources[0x65]	682514	1			T6	23		T7	1		T12	1
valid_sources[0x66]	711527	1			T6	11		T12	3		T1	269
valid_sources[0x67]	693831	1			T4	5		T6	19		T7	6
valid_sources[0x68]	717574	1			T4	1		T6	4		T12	4
valid_sources[0x69]	708117	1			T4	2		T6	15		T7	3
valid_sources[0x6a]	726569	1			T4	1		T6	21		T12	6
valid_sources[0x6b]	690614	1			T6	10		T7	9		T12	4
valid_sources[0x6c]	695507	1			T4	6		T6	5		T7	1
valid_sources[0x6d]	695491	1			T6	7		T7	5		T12	3
valid_sources[0x6e]	711397	1			T4	3		T6	6		T12	4
valid_sources[0x6f]	715768	1			T6	21		T7	2		T12	6
valid_sources[0x70]	688871	1			T4	5		T6	15		T7	6
valid_sources[0x71]	719515	1			T4	2		T6	16		T7	9
valid_sources[0x72]	709530	1			T4	1		T6	11		T12	3
valid_sources[0x73]	667812	1			T4	6		T6	9		T7	11
valid_sources[0x74]	697662	1			T6	25		T12	4		T1	271
valid_sources[0x75]	705990	1			T4	1		T6	10		T12	3
valid_sources[0x76]	715007	1			T4	5		T6	9		T7	9
valid_sources[0x77]	712127	1			T4	2		T6	17		T7	9
valid_sources[0x78]	714082	1			T4	1		T6	16		T7	3
valid_sources[0x79]	671353	1			T4	1		T6	23		T7	10
valid_sources[0x7a]	700458	1			T4	3		T6	15		T7	5
valid_sources[0x7b]	714841	1			T6	30		T7	8		T1	264
valid_sources[0x7c]	750668	1			T6	21		T7	14		T12	12
valid_sources[0x7d]	716623	1			T4	2		T6	13		T7	10
valid_sources[0x7e]	726659	1			T4	4		T6	32		T7	2
valid_sources[0x7f]	707605	1			T4	1		T6	7		T12	3
valid_sources[0x80]	699741	1			T6	4		T7	10		T1	253

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7218034

1

T4

152

T6

60

T7

14

values[0x0]

all_enables

biggest_size

5908242

1

T4

63

T5

5

T6

27

values[0x1]

all_enables

biggest_size

5894902

1

T4

47

T5

3

T6

20