Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

162285233

1

T4

398

T5

16

T6

3357

full_word

19020372

1

T4

262

T5

8

T6

107

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	181305215	1			T4	660		T5	24		T6	3464
auto[TlIntgErrCmd]	136	1			T84	7		T85	13		T117	8
auto[TlIntgErrData]	132	1			T84	3		T85	10		T117	5
auto[TlIntgErrBoth]	122	1			T84	10		T85	7		T117	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169162322

1

T4

544

T5

1

T6

3406

auto[1]

12143283

1

T4

116

T5

23

T6

58

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	161944061	1			T4	392		T5	1		T6	3346
auto[TlIntgErrNone]	partial	auto[1]	340810	1			T4	6		T5	15		T6	11
auto[TlIntgErrNone]	full_word	auto[0]	7218090	1			T4	152		T6	60		T7	14
auto[TlIntgErrNone]	full_word	auto[1]	11802254	1			T4	110		T5	8		T6	47
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T84	3		T85	5		T117	3
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T84	2		T85	7		T117	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T84	1		T141	1		T202	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T84	1		T85	1		T203	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T84	1		T85	4		T117	3
auto[TlIntgErrData]	partial	auto[1]	68	1			T84	2		T85	5		T117	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T85	1		T200	1		T204	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T141	1		T203	1		T205	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T84	3		T85	3		T117	4
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T84	5		T85	3		T117	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T85	1		T141	1		T201	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T84	2		T139	1		T205	1