Line Coverage for Module :
prim_generic_flop
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Module :
prim_generic_flop
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_sync_rxf.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_sync_rxf.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_sync_rxf.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_sync_rxf.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_sync_txe.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_sync_txe.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_sync_txe.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_sync_txe.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_rxf_overflow.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_rxf_overflow.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_rxf_overflow.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_rxf_overflow.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_txf_underflow.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_txf_underflow.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_txf_underflow.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_txf_underflow.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T1 |
Line Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T1 |
Line Coverage for Instance : tb.dut.u_csb_edge_sysclk.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_csb_edge_sysclk.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_csb_edge_sysclk.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_csb_edge_sysclk.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_csb_edge_spiclk.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_csb_edge_spiclk.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T7,T12,T1 |
Line Coverage for Instance : tb.dut.u_csb_edge_spiclk.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_csb_edge_spiclk.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T7,T12,T1 |
Line Coverage for Instance : tb.dut.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_sck_csb_edge.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_sck_csb_edge.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T1 |
Line Coverage for Instance : tb.dut.u_sck_csb_edge.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_sck_csb_edge.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T1 |
Line Coverage for Instance : tb.dut.u_clk_csb_edge_0.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_csb_edge_0.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_clk_csb_edge_0.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_clk_csb_edge_0.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_sck_tog_edge.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_sck_tog_edge.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T1 |
Line Coverage for Instance : tb.dut.u_sck_tog_edge.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_sck_tog_edge.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T1 |
Line Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_fwmode.u_rx_fifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_fwmode.u_tx_fifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T7,T12,T1 |
Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T7 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T1 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo.sync_wptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T1 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo.sync_rptr.u_sync_1.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T1 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| ALWAYS | 18 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 18 |
1 |
1 |
| 19 |
1 |
1 |
| 21 |
1 |
1 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo.sync_rptr.u_sync_2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
18 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 18 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T6,T1 |