Unified Coverage Report :: Module :: spi_tpm

Module : spi_tpm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.87	99.52	93.66		91.67	94.50	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm	95.87	99.52	93.66		91.67	94.50	100.00

---

Module Instance : tb.dut.u_spi_tpm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.87	99.52	93.66		91.67	94.50	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	99.76	93.53		91.67	97.18	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cmdaddr_buffer	98.08	100.00	92.31			100.00	100.00
u_hw_reg_slice	100.00	100.00					100.00
u_rdfifo	98.44	100.00	93.75			100.00	100.00
u_wrfifo	98.44	100.00	93.75			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spi_tpm

	Line No.	Total	Covered	Percent
TOTAL		209	208	99.52
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
ALWAYS	466	8	8	100.00
ALWAYS	483	3	3	100.00
ALWAYS	496	4	4	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
ALWAYS	537	3	3	100.00
ALWAYS	545	4	4	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	555	1	1	100.00
ALWAYS	560	6	6	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
ALWAYS	588	4	4	100.00
CONT_ASSIGN	595	1	1	100.00
ALWAYS	598	4	4	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	607	1	1	100.00
ALWAYS	612	5	5	100.00
ALWAYS	640	4	4	100.00
ALWAYS	653	6	6	100.00
ALWAYS	670	6	6	100.00
ALWAYS	686	3	3	100.00
ALWAYS	692	6	6	100.00
ALWAYS	703	4	4	100.00
ALWAYS	713	4	4	100.00
ALWAYS	722	4	4	100.00
CONT_ASSIGN	729	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
ALWAYS	740	7	7	100.00
ALWAYS	782	15	15	100.00
ALWAYS	859	3	3	100.00
CONT_ASSIGN	868	1	1	100.00
ALWAYS	871	3	3	100.00
CONT_ASSIGN	891	1	1	100.00
CONT_ASSIGN	892	1	1	100.00
CONT_ASSIGN	897	1	1	100.00
CONT_ASSIGN	910	1	1	100.00
ALWAYS	914	4	4	100.00
CONT_ASSIGN	922	1	1	100.00
ALWAYS	946	3	3	100.00
ALWAYS	954	68	67	98.53
CONT_ASSIGN	1208	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
310	1	1
324	1	1
348	1	1
354	1	1
455	1	1
456	1	1
462	1	1
466	1	1
467	1	1
468	1	1
470	1	1
471	1	1
472	1	1
473	1	1
474	1	1
			MISSING_ELSE
483	1	1
484	1	1
486	1	1
496	1	1
497	1	1
498	1	1
499	1	1
			MISSING_ELSE
505	1	1
507	1	1
509	1	1
534	1	1
537	1	1
538	1	1
540	1	1
545	1	1
546	1	1
547	1	1
548	1	1
			MISSING_ELSE
552	1	1
555	1	1
560	1	1
561	1	1
562	1	1
564	1	1
565	1	1
566	1	1
			MISSING_ELSE
577	1	1
584	1	1
588	1	1
589	1	1
590	1	1
591	1	1
			MISSING_ELSE
595	1	1
598	1	1
599	1	1
600	1	1
601	1	1
			MISSING_ELSE
605	1	1
607	1	1
612	1	1
613	1	1
617	1	1
624	1	1
630	1	1
640	1	1
641	1	1
642	1	1
644	1	1
			MISSING_ELSE
653	1	1
654	1	1
655	1	1
656	1	1
664	1	1
665	1	1
			MISSING_ELSE
670	1	1
671	1	1
673	1	1
674	1	1
675	1	1
676	1	1
			MISSING_ELSE
686	2	2
687	1	1
692	1	1
693	1	1
694	1	1
695	1	1
696	1	1
697	1	1
			MISSING_ELSE
703	1	1
704	1	1
705	1	1
707	1	1
			MISSING_ELSE
713	1	1
714	1	1
715	1	1
716	1	1
			MISSING_ELSE
722	1	1
723	1	1
724	1	1
726	1	1
			MISSING_ELSE
729	1	1
730	1	1
733	1	1
740	1	1
742	1	1
744	1	1
748	1	1
752	1	1
756	1	1
760	1	1
782	1	1
784	1	1
786	1	1
787	1	1
788	1	1
			MISSING_ELSE
795	1	1
799	1	1
803	1	1
807	1	1
812	1	1
814	1	1
816	1	1
821	1	1
825	1	1
829	1	1
859	1	1
860	1	1
862	1	1
868	1	1
871	2	2
872	1	1
891	1	1
892	1	1
897	1	1
910	1	1
914	1	1
915	1	1
916	1	1
917	1	1
			MISSING_ELSE
922	1	1
946	1	1
947	1	1
949	1	1
954	1	1
957	1	1
958	1	1
960	1	1
961	1	1
962	1	1
964	1	1
965	1	1
971	1	1
973	1	1
975	1	1
977	1	1
978	1	1
979	1	1
981	1	1
989	0	1
			MISSING_ELSE
996	1	1
999	1	1
1000	1	1
			MISSING_ELSE
1003	1	1
1005	1	1
1006	1	1
			MISSING_ELSE
1010	1	1
1011	1	1
1014	1	1
1016	1	1
1017	1	1
1020	1	1
1021	1	1
1024	1	1
1027	1	1
1029	1	1
			MISSING_ELSE
1033	1	1
1035	1	1
1037	1	1
1042	1	1
1046	1	1
			MISSING_ELSE
1052	1	1
1053	1	1
1056	1	1
1059	1	1
			MISSING_ELSE
1064	1	1
1065	1	1
1067	1	1
1069	1	1
1070	1	1
1071	1	1
1072	1	1
1073	1	1
1074	1	1
			==> MISSING_ELSE
			MISSING_ELSE
1080	1	1
1082	1	1
1083	1	1
1088	1	1
1089	1	1
			MISSING_ELSE
1094	1	1
1095	1	1
1099	1	1
1100	1	1
			MISSING_ELSE
1105	1	1
1109	1	1
1110	1	1
			MISSING_ELSE
1116	1	1
1117	1	1
1118	1	1
			==> MISSING_ELSE
1125	1	1
1126	1	1
1127	1	1
			MISSING_ELSE
1208	1	1

---

Cond Coverage for Module : spi_tpm

	Total	Covered	Percent
Conditions	142	133	93.66
Logical	142	133	93.66
Non-Logical	0	0
Event	0	0

 LINE       505
 EXPRESSION ((cmdaddr_bitcnt == 5'b0) && (sck_st_q == StIdle))
             ------------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T5,T6

 LINE       505
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'b0)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       505
 SUB-EXPRESSION (sck_st_q == StIdle)
                ----------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       507
 EXPRESSION (cmdaddr_bitcnt == 5'h0f)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       509
 EXPRESSION (cmdaddr_bitcnt == 5'h1d)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       534
 EXPRESSION (cmdaddr_bitcnt == 5'h1f)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       584
 EXPRESSION (isck_p2s_sent && (isck_data_sel == SelHwReg))
             ------1------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T103,T9
1	0	Covered	T4,T6,T1
1	1	Covered	T8,T103,T9

 LINE       584
 SUB-EXPRESSION (isck_data_sel == SelHwReg)
                -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T103,T9

 LINE       595
 EXPRESSION (wrdata_bitcnt == 3'h7)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       642
 EXPRESSION (check_tpm_reg && (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr)))
             ------1------    ------------------------------2------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T8,T31,T9
1	1	Covered	T4,T6,T1

 LINE       642
 SUB-EXPRESSION (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr))
                 ---------------1---------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T1
0	1	Covered	T4,T8,T31
1	0	Covered	T6,T1,T31

 LINE       642
 SUB-EXPRESSION (addr[23:16] == TpmAddr)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T1,T8

 LINE       656
 EXPRESSION (((!sys_clk_tpm_cfg.tpm_mode)) && check_hw_reg && (cmd_type == Read) && is_tpm_reg && ((!invalid_locality)) && ((!sys_clk_tpm_cfg.hw_reg_dis)))
             --------------1--------------    ------2-----    ---------3--------    -----4----    ----------5----------    ---------------6---------------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	1	1	1	1	1	Covered	T6,T1,T31
1	0	1	1	1	1	Covered	T8,T103,T9
1	1	0	1	1	1	Covered	T8,T9,T39
1	1	1	0	1	1	Covered	T8,T9,T39
1	1	1	1	0	1	Covered	T8,T9,T39
1	1	1	1	1	0	Covered	T8,T9,T39
1	1	1	1	1	1	Covered	T8,T103,T9

 LINE       656
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T6,T1

 LINE       674
 EXPRESSION (TpmReturnByHwAddr[i][11:2] == addr[11:2])
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       695
 EXPRESSION (latch_locality && is_tpm_reg)
             -------1------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T8,T31,T9
1	1	Covered	T4,T6,T1

 LINE       697
 EXPRESSION ((addr[15:12] < 4'(spi_device_reg_pkg::NumLocality)) ? 1'b0 : 1'b1)
             -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T6,T1,T8
1	Covered	T4,T6,T1

 LINE       724
 EXPRESSION ((isck_p2s_sent && sck_rddata_shift_en) || (sck_wrfifo_wvalid && wrdata_shift_en))
             -------------------1------------------    -------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T1
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1

 LINE       724
 SUB-EXPRESSION (isck_p2s_sent && sck_rddata_shift_en)
                 ------1------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       724
 SUB-EXPRESSION (sck_wrfifo_wvalid && wrdata_shift_en)
                 --------1--------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Not Covered
1	1	Covered	T4,T6,T1

 LINE       730
 EXPRESSION (xfer_bytes_q == xfer_size)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       733
 EXPRESSION ((7'({isck_rdfifo_rdepth, 2'(0)}) > {1'b0, xfer_size}) | (7'(RdFifoSize) <= 7'(xfer_size)))
             --------------------------1--------------------------   ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Not Covered
1	0	Covered	T4,T6,T1

 LINE       787
 EXPRESSION (((!invalid_locality)) && (4'(i) == locality))
             ----------1----------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       787
 SUB-EXPRESSION (4'(i) == locality)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       812
 EXPRESSION (((!invalid_locality)) && sys_active_locality[locality[2:0]])
             ----------1----------    -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T103,T9,T39
1	1	Covered	T103,T9,T39

 LINE       868
 EXPRESSION (isck_p2s_valid && (isck_p2s_bitcnt == '0))
             -------1------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       868
 SUB-EXPRESSION (isck_p2s_bitcnt == '0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       897
 EXPRESSION (isck_rdfifo_rvalid && isck_p2s_sent && (isck_data_sel == SelRdFifo))
             ---------1--------    ------2------    --------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T1
1	1	0	Covered	T4,T6,T1
1	1	1	Covered	T4,T6,T1

 LINE       897
 SUB-EXPRESSION (isck_data_sel == SelRdFifo)
                --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       922
 EXPRESSION (isck_rd_byte_sent && ((&isck_rdfifo_idx)))
             --------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       977
 EXPRESSION (cmdaddr_bitcnt == 5'h07)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       999
 EXPRESSION (cmdaddr_bitcnt == 5'h13)
            ------------1------------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T6,T1

 LINE       1010
 EXPRESSION ((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Read))
             ------------1------------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       1010
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'h1f)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T6,T1

 LINE       1010
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T6,T1

 LINE       1011
 EXPRESSION (((!is_tpm_reg)) || sys_clk_tpm_cfg.tpm_mode)
             -------1-------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T8,T103,T9
0	1	Covered	T4,T6,T1
1	0	Covered	T8,T9,T39

 LINE       1021
 EXPRESSION (invalid_locality && sys_clk_tpm_cfg.invalid_locality)
             --------1-------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T39
1	0	Covered	T9,T39,T47
1	1	Covered	T8,T9,T39

 LINE       1033
 EXPRESSION ((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Write))
             ------------1------------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       1033
 SUB-EXPRESSION (cmdaddr_bitcnt == 5'h1f)
                ------------1------------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T6,T1

 LINE       1033
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T6,T1

 LINE       1056
 EXPRESSION (isck_p2s_sent && (((cmd_type == Read) && enough_payload_in_rdfifo) || ((cmd_type == Write) && ((~|sck_wrfifo_wdepth)))))
             ------1------    ---------------------------------------------------2--------------------------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       1056
 SUB-EXPRESSION (((cmd_type == Read) && enough_payload_in_rdfifo) || ((cmd_type == Write) && ((~|sck_wrfifo_wdepth))))
                 ------------------------1-----------------------    ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T1
0	1	Covered	T31,T9,T39
1	0	Covered	T4,T6,T1

 LINE       1056
 SUB-EXPRESSION ((cmd_type == Read) && enough_payload_in_rdfifo)
                 ---------1--------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       1056
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T31,T9,T39
1	Covered	T4,T6,T1

 LINE       1056
 SUB-EXPRESSION ((cmd_type == Write) && ((~|sck_wrfifo_wdepth)))
                 ---------1---------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T31,T9,T39
1	1	Covered	T31,T9,T39

 LINE       1056
 SUB-EXPRESSION (cmd_type == Write)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T31,T9,T39

 LINE       1069
 EXPRESSION ((cmd_type == Read) && is_hw_reg)
             ---------1--------    ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T8,T103,T9

 LINE       1069
 SUB-EXPRESSION (cmd_type == Read)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T6,T1

 LINE       1071
 EXPRESSION (cmd_type == Read)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T6,T1

 LINE       1073
 EXPRESSION (cmd_type == Write)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T1

 LINE       1088
 EXPRESSION (isck_p2s_sent && xfer_size_met)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       1099
 EXPRESSION (isck_p2s_sent && xfer_size_met)
             ------1------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T9,T47,T104
1	0	Covered	T8,T103,T9
1	1	Covered	T9,T47,T104

 LINE       1109
 EXPRESSION (sck_wrfifo_wvalid && xfer_size_met)
             --------1--------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       1116
 EXPRESSION (cmd_type == Read)
            ---------1--------

-1-	Status	Tests
0	Not Covered
1	Covered	T8,T9,T39

 LINE       1125
 EXPRESSION (cmd_type == Read)
            ---------1--------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T6,T1

---

FSM Coverage for Module : spi_tpm

Summary for FSM :: sck_st_q

	Total	Covered	Percent
States	9	9	100.00	(Not included in score)
Transitions	12	11	91.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: sck_st_q

---

states	Line No.	Covered	Tests
StAddr	979	Covered	T4,T6,T1
StEnd	989	Covered	T4,T6,T1
StIdle	974	Covered	T4,T5,T6
StInvalid	1024	Covered	T8,T9,T39
StReadFifo	1072	Covered	T4,T6,T1
StReadHwReg	1070	Covered	T8,T103,T9
StStartByte	1020	Covered	T4,T6,T1
StWait	1014	Covered	T4,T6,T1
StWrite	1074	Covered	T4,T6,T1

transitions	Line No.	Covered	Tests
StAddr->StInvalid	1024	Covered	T8,T9,T39
StAddr->StStartByte	1020	Covered	T4,T6,T1
StAddr->StWait	1014	Covered	T4,T6,T1
StIdle->StAddr	979	Covered	T4,T6,T1
StIdle->StEnd	989	Not Covered
StReadFifo->StEnd	1089	Covered	T4,T6,T1
StReadHwReg->StEnd	1100	Covered	T9,T47,T104
StStartByte->StReadFifo	1072	Covered	T4,T6,T1
StStartByte->StReadHwReg	1070	Covered	T8,T103,T9
StStartByte->StWrite	1074	Covered	T4,T6,T1
StWait->StStartByte	1059	Covered	T4,T6,T1
StWrite->StEnd	1110	Covered	T4,T6,T1

---

Branch Coverage for Module : spi_tpm

	Line No.	Total	Covered	Percent
Branches		109	103	94.50
IF	466	3	3	100.00
IF	483	2	2	100.00
IF	496	3	3	100.00
IF	537	2	2	100.00
IF	545	3	3	100.00
IF	560	4	4	100.00
IF	588	3	3	100.00
IF	598	3	3	100.00
CASE	613	4	4	100.00
IF	640	3	3	100.00
IF	653	3	3	100.00
IF	674	2	2	100.00
IF	686	2	2	100.00
IF	692	4	4	100.00
IF	703	3	3	100.00
IF	713	3	3	100.00
IF	722	3	3	100.00
CASE	742	6	5	83.33
CASE	784	11	10	90.91
IF	859	2	2	100.00
IF	871	2	2	100.00
IF	946	2	2	100.00
CASE	973	33	29	87.88
IF	914	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spi_tpm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	466	if ((!sys_rst_ni))
-2-:	470	if (sys_csb_pulse_stretch)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	483	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	496	if ((!rst_n))
-2-:	498	if (cmdaddr_shift_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	537	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	545	if ((!rst_n))
-2-:	547	if (cmdaddr_shift_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	560	if ((!rst_n))
-2-:	562	if (isck_fifoaddr_latch)
-3-:	565	if (isck_fifoaddr_inc)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T6,T1
0	0	1	Covered	T8,T103,T9
0	0	0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	588	if ((!rst_n))
-2-:	590	if (wrdata_shift_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	598	if ((!rst_n))
-2-:	600	if (wrdata_shift_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	613	case (1'b1)

Branches:

-1-	Status	Tests
check_tpm_reg	Covered	T4,T6,T1
latch_locality	Covered	T4,T6,T1
check_hw_reg	Covered	T4,T6,T1
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	640	if ((!rst_n))
-2-:	642	if ((check_tpm_reg && (sys_clk_tpm_cfg.tpm_reg_chk_dis || (addr[23:16] == TpmAddr))))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	653	if ((!rst_n))
-2-:	656	if (((((((!sys_clk_tpm_cfg.tpm_mode) && check_hw_reg) && (cmd_type == Read)) && is_tpm_reg) && (!invalid_locality)) && (!sys_clk_tpm_cfg.hw_reg_dis)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T8,T103,T9
0	0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	674	if ((TpmReturnByHwAddr[i][11:2] == addr[11:2]))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	686	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	692	if ((!rst_n))
-2-:	695	if ((latch_locality && is_tpm_reg))
-3-:	697	((addr[15:12] < 4'(spi_device_reg_pkg::NumLocality))) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	1	Covered	T4,T6,T1
0	1	0	Covered	T6,T1,T8
0	0	-	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	703	if ((!rst_n))
-2-:	705	if (latch_cmd_type)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	713	if ((!rst_n))
-2-:	715	if (latch_xfer_size)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	722	if ((!rst_n))
-2-:	724	if (((isck_p2s_sent && sck_rddata_shift_en) || (sck_wrfifo_wvalid && wrdata_shift_en)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	742	case (isck_data_sel)

Branches:

-1-	Status	Tests
SelWait	Covered	T4,T5,T6
SelStart	Covered	T4,T6,T1
SelInvalid	Covered	T8,T9,T39
SelHwReg	Covered	T8,T103,T9
SelRdFifo	Covered	T4,T6,T1
default	Not Covered

	LineNo.	Expression
-1-:	784	case (isck_hw_reg_idx)
-2-:	812	if (((!invalid_locality) && sys_active_locality[locality[2:0]]))

Branches:

-1-	-2-	Status	Tests
RegAccess	-	Covered	T4,T5,T6
RegIntEn	-	Covered	T9,T47,T104
RegIntVect	-	Covered	T9,T39,T47
RegIntSts	-	Covered	T8,T9,T39
RegIntfCap	-	Covered	T105,T106,T107
RegSts	1	Covered	T103,T9,T39
RegSts	0	Covered	T103,T9,T39
RegHashStart	-	Covered	T9,T47,T104
RegId	-	Covered	T8,T9,T39
RegRid	-	Covered	T8,T9,T39
default	-	Not Covered

	LineNo.	Expression
-1-:	859	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	871	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	946	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	973	case (sck_st_q)
-2-:	977	if ((cmdaddr_bitcnt == 5'h07))
-3-:	978	if (sys_clk_tpm_en)
-4-:	999	if ((cmdaddr_bitcnt == 5'h13))
-5-:	1003	if ((cmdaddr_bitcnt >= 5'h18))
-6-:	1010	if (((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Read)))
-7-:	1011	if (((!is_tpm_reg) || sys_clk_tpm_cfg.tpm_mode))
-8-:	1017	if (is_hw_reg)
-9-:	1021	if ((invalid_locality && sys_clk_tpm_cfg.invalid_locality))
-10-:	1033	if (((cmdaddr_bitcnt == 5'h1f) && (cmd_type == Write)))
-11-:	1037	if ((~|sck_wrfifo_wdepth))
-12-:	1056	if ((isck_p2s_sent && (((cmd_type == Read) && enough_payload_in_rdfifo) || ((cmd_type == Write) && (~|sck_wrfifo_wdepth)))))
-13-:	1067	if (isck_p2s_sent)
-14-:	1069	if (((cmd_type == Read) && is_hw_reg))
-15-:	1071	if ((cmd_type == Read))
-16-:	1073	if ((cmd_type == Write))
-17-:	1088	if ((isck_p2s_sent && xfer_size_met))
-18-:	1099	if ((isck_p2s_sent && xfer_size_met))
-19-:	1109	if ((sck_wrfifo_wvalid && xfer_size_met))
-20-:	1116	if ((cmd_type == Read))
-21-:	1125	if ((cmd_type == Read))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	Status	Tests
StIdle	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T1
StIdle	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StAddr	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T1
StAddr	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T1
StAddr	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T1
StAddr	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T1
StAddr	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T1
StAddr	-	-	-	-	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T103,T9
StAddr	-	-	-	-	1	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T39
StAddr	-	-	-	-	1	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T39
StAddr	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T1
StAddr	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T1
StAddr	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T31,T9,T39
StAddr	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T1
StWait	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T1
StWait	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T1
StStartByte	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Covered	T8,T103,T9
StStartByte	-	-	-	-	-	-	-	-	-	-	-	1	0	1	-	-	-	-	-	-	Covered	T4,T6,T1
StStartByte	-	-	-	-	-	-	-	-	-	-	-	1	0	0	1	-	-	-	-	-	Covered	T4,T6,T1
StStartByte	-	-	-	-	-	-	-	-	-	-	-	1	0	0	0	-	-	-	-	-	Not Covered
StStartByte	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T6,T1
StReadFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T6,T1
StReadFifo	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T6,T1
StReadHwReg	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T9,T47,T104
StReadHwReg	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T8,T103,T9
StWrite	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T6,T1
StWrite	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T4,T6,T1
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T9,T39
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StEnd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T6,T1
StEnd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T6,T1
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	914	if ((!rst_n))
-2-:	916	if (isck_rd_byte_sent)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T6,T1

---

Assert Coverage for Module : spi_tpm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	18	18	100.00	18	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	18	18	100.00	18	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CmdAddrAvailable_A	394100318	63298	0	0
CmdAddrBitCntInAddrSt_A	394100318	726552	0	0
CmdAddrInfo_A	394100318	73858	0	0
CmdPowerof2_A	1601	1601	0	0
DataFifoLessThan64_A	1601	1601	0	0
DataSelKnown_A	394101543	35415598	0	0
HwRegCondition2_a	394100318	17305	0	0
HwRegCondition_A	394100318	90819	0	0
HwRegIdxKnown_A	394101543	35415598	0	0
LocalityLatchCondition_A	394100318	90819	0	0
RdFifoDepthPoT_A	1601	1601	0	0
RdFifoNumBytesPoT_A	1601	1601	0	0
RdPowerof2_A	1601	1601	0	0
SckFifoAddrLatchCondition_A	394100318	90819	0	0
TpmRegCondition_A	394100318	90819	0	0
TpmRegSizeMatch_A	1601	1601	0	0
WrDepthSpec_A	1601	1601	0	0
WrFifoAvailable_A	394100318	550238	0	0

CmdAddrAvailable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	63298	0	0
T1	884449	145	0	0
T2	377666	0	0	0
T3	1	0	0	0
T4	6904	17	0	0
T6	3017	14	0	0
T7	21468	0	0	0
T8	836914	51	0	0
T9	0	316	0	0
T10	385	0	0	0
T11	101282	0	0	0
T12	52863	0	0	0
T19	0	462	0	0
T31	0	350	0	0
T39	0	939	0	0
T40	0	225	0	0
T62	0	225	0	0

CmdAddrBitCntInAddrSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	726552	0	0
T1	884449	1160	0	0
T2	377666	0	0	0
T3	1	0	0	0
T4	6904	136	0	0
T6	3017	112	0	0
T7	21468	0	0	0
T8	836914	504	0	0
T9	0	3048	0	0
T10	385	0	0	0
T11	101282	0	0	0
T12	52863	0	0	0
T31	0	2800	0	0
T39	0	7792	0	0
T40	0	1800	0	0
T61	0	160	0	0
T103	0	96	0	0

CmdAddrInfo_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	73858	0	0
T1	884449	145	0	0
T2	377666	0	0	0
T3	1	0	0	0
T4	6904	17	0	0
T6	3017	14	0	0
T7	21468	0	0	0
T8	836914	31	0	0
T9	0	317	0	0
T10	385	0	0	0
T11	101282	0	0	0
T12	52863	0	0	0
T31	0	303	0	0
T39	0	755	0	0
T40	0	166	0	0
T61	0	20	0	0
T103	0	12	0	0

CmdPowerof2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

DataFifoLessThan64_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

DataSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394101543	35415598	0	0
T1	884450	45664	0	0
T2	377667	0	0	0
T3	1	0	0	0
T4	6905	6904	0	0
T5	1	0	0	0
T6	3018	2768	0	0
T7	21469	0	0	0
T8	836915	14528	0	0
T9	0	168264	0	0
T10	386	0	0	0
T12	52864	0	0	0
T31	0	263952	0	0
T39	0	521312	0	0
T40	0	65864	0	0
T61	0	1440	0	0
T103	0	864	0	0

HwRegCondition2_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	17305	0	0
T8	836914	6	0	0
T9	0	38	0	0
T10	385	0	0	0
T11	101282	0	0	0
T13	65808	0	0	0
T14	565090	0	0	0
T15	385	0	0	0
T31	268674	0	0	0
T36	113230	0	0	0
T39	0	18	0	0
T46	33	0	0	0
T47	0	55	0	0
T61	0	20	0	0
T103	864	12	0	0
T104	0	390	0	0
T108	0	9	0	0
T109	0	187	0	0
T110	0	63	0	0

HwRegCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	90819	0	0
T1	884449	145	0	0
T2	377666	0	0	0
T3	1	0	0	0
T4	6904	17	0	0
T6	3017	14	0	0
T7	21468	0	0	0
T8	836914	63	0	0
T9	0	381	0	0
T10	385	0	0	0
T11	101282	0	0	0
T12	52863	0	0	0
T31	0	350	0	0
T39	0	974	0	0
T40	0	225	0	0
T61	0	20	0	0
T103	0	12	0	0

HwRegIdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394101543	35415598	0	0
T1	884450	45664	0	0
T2	377667	0	0	0
T3	1	0	0	0
T4	6905	6904	0	0
T5	1	0	0	0
T6	3018	2768	0	0
T7	21469	0	0	0
T8	836915	14528	0	0
T9	0	168264	0	0
T10	386	0	0	0
T12	52864	0	0	0
T31	0	263952	0	0
T39	0	521312	0	0
T40	0	65864	0	0
T61	0	1440	0	0
T103	0	864	0	0

LocalityLatchCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	90819	0	0
T1	884449	145	0	0
T2	377666	0	0	0
T3	1	0	0	0
T4	6904	17	0	0
T6	3017	14	0	0
T7	21468	0	0	0
T8	836914	63	0	0
T9	0	381	0	0
T10	385	0	0	0
T11	101282	0	0	0
T12	52863	0	0	0
T31	0	350	0	0
T39	0	974	0	0
T40	0	225	0	0
T61	0	20	0	0
T103	0	12	0	0

RdFifoDepthPoT_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

RdFifoNumBytesPoT_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

RdPowerof2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

SckFifoAddrLatchCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	90819	0	0
T1	884449	145	0	0
T2	377666	0	0	0
T3	1	0	0	0
T4	6904	17	0	0
T6	3017	14	0	0
T7	21468	0	0	0
T8	836914	63	0	0
T9	0	381	0	0
T10	385	0	0	0
T11	101282	0	0	0
T12	52863	0	0	0
T31	0	350	0	0
T39	0	974	0	0
T40	0	225	0	0
T61	0	20	0	0
T103	0	12	0	0

TpmRegCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	90819	0	0
T1	884449	145	0	0
T2	377666	0	0	0
T3	1	0	0	0
T4	6904	17	0	0
T6	3017	14	0	0
T7	21468	0	0	0
T8	836914	63	0	0
T9	0	381	0	0
T10	385	0	0	0
T11	101282	0	0	0
T12	52863	0	0	0
T31	0	350	0	0
T39	0	974	0	0
T40	0	225	0	0
T61	0	20	0	0
T103	0	12	0	0

TpmRegSizeMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

WrDepthSpec_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

WrFifoAvailable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	550238	0	0
T1	884449	938	0	0
T2	377666	0	0	0
T3	1	0	0	0
T4	6904	283	0	0
T6	3017	106	0	0
T7	21468	0	0	0
T8	836914	284	0	0
T9	0	3473	0	0
T10	385	0	0	0
T11	101282	0	0	0
T12	52863	0	0	0
T19	0	3635	0	0
T31	0	3312	0	0
T39	0	7833	0	0
T40	0	2029	0	0
T62	0	1629	0	0