Unified Coverage Report :: Module :: prim_fifo_async

Module : prim_fifo_async

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	91.96			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_status.u_sw_status_update_sync	92.92	100.00	80.00			91.67	100.00
tb.dut.u_spi_tpm.u_cmdaddr_buffer	98.08	100.00	92.31			100.00	100.00
tb.dut.u_spi_tpm.u_wrfifo	98.44	100.00	93.75			100.00	100.00
tb.dut.u_spi_tpm.u_rdfifo	98.44	100.00	93.75			100.00	100.00
tb.dut.u_fwmode.u_rx_fifo	99.17	100.00	96.67			100.00	100.00
tb.dut.u_fwmode.u_tx_fifo	99.17	100.00	96.67			100.00	100.00

Line Coverage for Module : prim_fifo_async ( parameter Width=8,Depth=8,OutputZeroIfEmpty=0,OutputZeroIfInvalid=0,DepthW=4,PTRV_W=3,PTR_WIDTH=4 )
Line Coverage for Module self-instances :

SCORE	LINE
99.17	100.00

tb.dut.u_fwmode.u_rx_fifo

SCORE	LINE
99.17	100.00

tb.dut.u_fwmode.u_tx_fifo

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
ROUTINE	230	7	7	100.00
ROUTINE	251	9	9	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
214	1	1
230	1	1
232	1	1
235	1	1
236	1	1
239	1	1
240	1	1
243	1	1
251	1	1
252	1	1
253	1	1
255	1	1
256	1	1
257	1	1
259	1	1
260	1	1
262	1	1
267	1	1
269	1	1
271	1	1
272	1	1

---

Line Coverage for Module : prim_fifo_async ( parameter Width=24,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 + Width=32,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 )
Line Coverage for Module self-instances :

SCORE	LINE
92.92	100.00

tb.dut.u_spid_status.u_sw_status_update_sync

SCORE	LINE
98.08	100.00

tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
CONT_ASSIGN	276	1	1	100.00
CONT_ASSIGN	277	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
207	1	1
276	1	1
277	1	1
279	1	1
280	1	1

---

Line Coverage for Module : prim_fifo_async ( parameter Width=8,Depth=64,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=7,PTRV_W=6,PTR_WIDTH=7 )
Line Coverage for Module self-instances :

SCORE	LINE
98.44	100.00

tb.dut.u_spi_tpm.u_wrfifo

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
ROUTINE	230	7	7	100.00
ROUTINE	251	9	9	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
207	1	1
230	1	1
232	1	1
235	1	1
236	1	1
239	1	1
240	1	1
243	1	1
251	1	1
252	1	1
253	1	1
255	1	1
256	1	1
257	1	1
259	1	1
260	1	1
262	1	1
267	1	1
269	1	1
271	1	1
272	1	1

---

Line Coverage for Module : prim_fifo_async ( parameter Width=32,Depth=16,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=5,PTRV_W=4,PTR_WIDTH=5 )
Line Coverage for Module self-instances :

SCORE	LINE
98.44	100.00

tb.dut.u_spi_tpm.u_rdfifo

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
ALWAYS	59	4	4	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	92	4	4	100.00
ALWAYS	101	4	4	100.00
ALWAYS	117	3	3	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	146	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
ALWAYS	182	2	2	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	207	1	1	100.00
ROUTINE	230	7	7	100.00
ROUTINE	251	9	9	100.00
CONT_ASSIGN	267	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
53	1	1
56	1	1
59	1	1
60	1	1
61	1	1
62	1	1
			MISSING_ELSE
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
86	1	1
89	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
101	1	1
102	1	1
103	1	1
104	1	1
			MISSING_ELSE
117	1	1
118	1	1
120	1	1
130	1	1
131	1	1
132	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	1	1
171	1	1
172	1	1
182	1	1
183	1	1
			MISSING_ELSE
187	1	1
207	1	1
230	1	1
232	1	1
235	1	1
236	1	1
239	1	1
240	1	1
243	1	1
251	1	1
252	1	1
253	1	1
255	1	1
256	1	1
257	1	1
259	1	1
260	1	1
262	1	1
267	1	1
269	1	1
271	1	1
272	1	1

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=8,Depth=8,OutputZeroIfEmpty=0,OutputZeroIfInvalid=0,DepthW=4,PTRV_W=3,PTR_WIDTH=4 )
Cond Coverage for Module self-instances :

SCORE	COND
99.17	96.67

tb.dut.u_fwmode.u_rx_fifo

SCORE	COND
99.17	96.67

tb.dut.u_fwmode.u_tx_fifo

	Total	Covered	Percent
Conditions	30	30	100.00
Logical	30	30	100.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T10,T15,T33
1	1	Covered	T2,T3,T10

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T33,T9,T49
1	0	Covered	T2,T10,T11
1	1	Covered	T2,T10,T11

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T10

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T10,T11

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (4'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((4'(g_depth_calc.wptr_value) - 4'(g_depth_calc.rptr_sync_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_sync_value)) + 4'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T10

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((4'(g_depth_calc.wptr_value) - 4'(g_depth_calc.rptr_sync_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_sync_value)) + 4'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T2,T10,T11
1	Covered	T4,T5,T6

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T4,T5,T6

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (4'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((4'(g_depth_calc.wptr_sync_value) - 4'(g_depth_calc.rptr_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_value)) + 4'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T10,T11

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((4'(g_depth_calc.wptr_sync_value) - 4'(g_depth_calc.rptr_value))) : (((4'(Depth) - 4'(g_depth_calc.rptr_value)) + 4'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T2,T10,T11
1	Covered	T4,T5,T6

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T2,T10,T11
1	Covered	T4,T5,T6

 LINE       232
 EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
             -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T10

 LINE       253
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T10,T11
1	0	Covered	T2,T10,T11
1	1	Covered	T2,T10,T11

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=8,Depth=64,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=7,PTRV_W=6,PTR_WIDTH=7 )
Cond Coverage for Module self-instances :

SCORE	COND
98.44	93.75

tb.dut.u_spi_tpm.u_wrfifo

	Total	Covered	Percent
Conditions	32	30	93.75
Logical	32	30	93.75
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T6,T1

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T9,T39

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T9,T39

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (7'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((7'(g_depth_calc.wptr_value) - 7'(g_depth_calc.rptr_sync_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_sync_value)) + 7'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T9,T39

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((7'(g_depth_calc.wptr_value) - 7'(g_depth_calc.rptr_sync_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_sync_value)) + 7'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (7'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((7'(g_depth_calc.wptr_sync_value) - 7'(g_depth_calc.rptr_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_value)) + 7'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T31,T9,T39

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((7'(g_depth_calc.wptr_sync_value) - 7'(g_depth_calc.rptr_value))) : (((7'(Depth) - 7'(g_depth_calc.rptr_value)) + 7'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       232
 EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
             -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       253
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=32,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Total	Covered	Percent
Conditions	26	24	92.31
Logical	26	24	92.31
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T6,T1

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T31

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T31

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T31

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T31

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=24,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 )
Cond Coverage for Module self-instances :

SCORE	COND
92.92	80.00

tb.dut.u_spid_status.u_sw_status_update_sync

	Total	Covered	Percent
Conditions	25	20	80.00
Logical	25	20	80.00
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T7,T1,T8

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T7,T1,T8

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T4,T5,T6

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T4,T5,T6

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Not Covered

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T4,T5,T6

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T4,T5,T6

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Covered	T7,T1,T8
1	Covered	T4,T5,T6

---

Cond Coverage for Module : prim_fifo_async ( parameter Width=32,Depth=16,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=5,PTRV_W=4,PTR_WIDTH=5 )
Cond Coverage for Module self-instances :

SCORE	COND
98.44	93.75

tb.dut.u_spi_tpm.u_rdfifo

	Total	Covered	Percent
Conditions	32	30	93.75
Logical	32	30	93.75
Non-Logical	0	0
Event	0	0

 LINE       53
 EXPRESSION (wvalid_i & wready_o)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T6,T1

 LINE       86
 EXPRESSION (rvalid_o & rready_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       130
 EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T1,T8

 LINE       131
 EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T1,T8

 LINE       132
 EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
            ------------------1------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       146
 EXPRESSION 
 Number  Term
      1  full_wclk ? (5'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((5'(g_depth_calc.wptr_value) - 5'(g_depth_calc.rptr_sync_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_sync_value)) + 5'(g_depth_calc.wptr_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T1,T8

 LINE       146
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((5'(g_depth_calc.wptr_value) - 5'(g_depth_calc.rptr_sync_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_sync_value)) + 5'(g_depth_calc.wptr_value))))

-1-	Status	Tests
0	Covered	T4,T1,T8
1	Covered	T4,T5,T6

 LINE       146
 SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T1,T8
1	Covered	T4,T5,T6

 LINE       160
 EXPRESSION 
 Number  Term
      1  full_rclk ? (5'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((5'(g_depth_calc.wptr_sync_value) - 5'(g_depth_calc.rptr_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_value)) + 5'(g_depth_calc.wptr_sync_value)))))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T1,T8

 LINE       160
 SUB-EXPRESSION 
 Number  Term
      1  (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((5'(g_depth_calc.wptr_sync_value) - 5'(g_depth_calc.rptr_value))) : (((5'(Depth) - 5'(g_depth_calc.rptr_value)) + 5'(g_depth_calc.wptr_sync_value))))

-1-	Status	Tests
0	Covered	T4,T1,T8
1	Covered	T4,T5,T6

 LINE       160
 SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
                --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T4,T1,T8
1	Covered	T4,T5,T6

 LINE       207
 EXPRESSION (empty_rclk ? '0 : rdata_int)
             -----1----

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       232
 EXPRESSION (decval[(PTR_WIDTH - 1)] ? decval_sub : decval)
             -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       253
 EXPRESSION (dec_tmp[(i + 1)] ^ grayval[i])
             --------1-------   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

---

Branch Coverage for Module : prim_fifo_async ( parameter Width=24,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 + Width=32,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
92.92	91.67

tb.dut.u_spid_status.u_sw_status_update_sync

SCORE	BRANCH
98.08	100.00

tb.dut.u_spi_tpm.u_cmdaddr_buffer

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	146	3	3	100.00
TERNARY	160	3	3	100.00
TERNARY	207	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	182	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T8,T31
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T8,T31
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	207	(empty_rclk) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T7
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T7
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T7
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T7
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T4,T5,T6

---

Branch Coverage for Module : prim_fifo_async ( parameter Width=8,Depth=8,OutputZeroIfEmpty=0,OutputZeroIfInvalid=0,DepthW=4,PTRV_W=3,PTR_WIDTH=4 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.17	100.00

tb.dut.u_fwmode.u_rx_fifo

SCORE	BRANCH
99.17	100.00

tb.dut.u_fwmode.u_tx_fifo

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
TERNARY	146	3	3	100.00
TERNARY	160	3	3	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	182	2	2	100.00
TERNARY	232	2	2	100.00
IF	256	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T10
0	1	Covered	T4,T5,T6
0	0	Covered	T2,T10,T11

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T10,T11
0	1	Covered	T4,T5,T6
0	0	Covered	T2,T10,T11

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T3,T10
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T3,T10
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T10,T11
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T10,T11
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	232	(decval[(PTR_WIDTH - 1)]) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	256	if (grayval[(PTR_WIDTH - 1)])

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T11
0	Covered	T4,T5,T6

---

Branch Coverage for Module : prim_fifo_async ( parameter Width=8,Depth=64,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=7,PTRV_W=6,PTR_WIDTH=7 + Width=32,Depth=16,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=5,PTRV_W=4,PTR_WIDTH=5 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.44	100.00

tb.dut.u_spi_tpm.u_wrfifo

SCORE	BRANCH
98.44	100.00

tb.dut.u_spi_tpm.u_rdfifo

	Line No.	Total	Covered	Percent
Branches		28	28	100.00
TERNARY	146	3	3	100.00
TERNARY	160	3	3	100.00
TERNARY	207	2	2	100.00
IF	59	3	3	100.00
IF	68	3	3	100.00
IF	92	3	3	100.00
IF	101	3	3	100.00
IF	117	2	2	100.00
IF	182	2	2	100.00
TERNARY	232	2	2	100.00
IF	256	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_async.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	146	(full_wclk) ? 
-2-:	146	((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T8
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	160	(full_rclk) ? 
-2-:	160	((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T8
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	207	(empty_rclk) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T6,T1

	LineNo.	Expression
-1-:	59	if ((!rst_wr_ni))
-2-:	61	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	68	if ((!rst_wr_ni))
-2-:	70	if (fifo_incr_wptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	92	if ((!rst_rd_ni))
-2-:	94	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	101	if ((!rst_rd_ni))
-2-:	103	if (fifo_incr_rptr)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T6,T1
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	117	if ((!rst_wr_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	182	if (fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	232	(decval[(PTR_WIDTH - 1)]) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	256	if (grayval[(PTR_WIDTH - 1)])

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T1
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_fifo_async

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GrayRptr_A	2147483647	2147483647	0	0
GrayWptr_A	2147483647	2147483647	0	0
ParamCheckDepth_A	9606	9606	0	0

GrayRptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4078520	3239569	0	0
T2	2178458	1800772	0	0
T3	3562	3366	0	0
T4	33962	33810	0	0
T5	2300	2154	0	0
T6	42094	41722	0	0
T7	117864	96229	0	0
T8	4382566	3560096	0	0
T9	0	167883	0	0
T10	6278	5584	0	0
T11	426262	527541	0	0
T12	324856	271860	0	0
T13	0	131614	0	0
T31	0	263602	0	0
T39	0	520338	0	0
T40	0	65639	0	0
T61	0	1420	0	0
T103	0	852	0	0

GrayWptr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	4078518	3945049	0	0
T2	2178456	1829956	0	0
T3	3562	2240	0	0
T4	33960	32984	0	0
T5	2298	1077	0	0
T6	42092	40869	0	0
T7	117862	101782	0	0
T8	4382564	3952328	0	0
T10	6276	4426	0	0
T11	628826	628822	0	0
T12	324854	268085	0	0
T13	0	197421	0	0
T31	0	87344	0	0
T32	0	6920	0	0
T35	0	1449	0	0
T81	0	99	0	0
T103	0	264	0	0
T111	0	245	0	0

ParamCheckDepth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9606	9606	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T6	6	6	0	0
T7	6	6	0	0
T8	6	6	0	0
T10	6	6	0	0
T12	6	6	0	0