Unified Coverage Report :: Module :: prim_edge_detector

Module : prim_edge_detector

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_csb_edge_spiclk	94.44	100.00	83.33			100.00
tb.dut.u_sck_csb_edge	94.44	100.00	83.33			100.00
tb.dut.u_intr_upload_edge	100.00	100.00				100.00
tb.dut.u_csb_edge_sysclk	100.00	100.00	100.00			100.00
tb.dut.u_clk_csb_edge_0	100.00	100.00	100.00			100.00
tb.dut.u_sck_tog_edge	100.00	100.00	100.00			100.00
tb.dut.u_readcmd.u_addr_latch_pulse	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_csb_edge_spiclk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_sync.u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sck_csb_edge

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_sync.u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_intr_upload_edge

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_csb_edge_sysclk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_sync.u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_csb_edge_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_sync.u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_sck_tog_edge

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.39	96.31	94.03	97.00		93.33	96.30	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_sync.u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_readcmd.u_addr_latch_pulse

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.19	96.32	100.00		80.00	84.62	100.00	u_readcmd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_edge_detector ( parameter Width=2,ResetValue=0,EnSync=0 + Width=1,ResetValue=0,EnSync=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_intr_upload_edge

SCORE	LINE
100.00	100.00

tb.dut.u_readcmd.u_addr_latch_pulse

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
45	1	1
48	2	2
49	1	1
52	1	1
53	1	1

---

Line Coverage for Module : prim_edge_detector ( parameter Width=1,ResetValue,EnSync=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_csb_edge_sysclk

SCORE	LINE
94.44	100.00

tb.dut.u_csb_edge_spiclk

SCORE	LINE
94.44	100.00

tb.dut.u_sck_csb_edge

SCORE	LINE
100.00	100.00

tb.dut.u_clk_csb_edge_0

SCORE	LINE
100.00	100.00

tb.dut.u_sck_tog_edge

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
48	2	2
49	1	1
52	1	1
53	1	1

---

Cond Coverage for Module : prim_edge_detector

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T6,T7

---

Branch Coverage for Module : prim_edge_detector

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_csb_edge_spiclk

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
48	2	2
49	1	1
52	1	1
53	1	1

---

Cond Coverage for Instance : tb.dut.u_csb_edge_spiclk

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T1
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T12,T1
1	1	Covered	T7,T12,T1

---

Branch Coverage for Instance : tb.dut.u_csb_edge_spiclk

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T7,T12,T1

Line Coverage for Instance : tb.dut.u_sck_csb_edge

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
48	2	2
49	1	1
52	1	1
53	1	1

---

Cond Coverage for Instance : tb.dut.u_sck_csb_edge

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Not Covered

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

---

Branch Coverage for Instance : tb.dut.u_sck_csb_edge

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T6,T1

Line Coverage for Instance : tb.dut.u_intr_upload_edge

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
45	1	1
48	2	2
49	1	1
52	1	1
53	1	1

---

Branch Coverage for Instance : tb.dut.u_intr_upload_edge

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_csb_edge_sysclk

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
48	2	2
49	1	1
52	1	1
53	1	1

---

Cond Coverage for Instance : tb.dut.u_csb_edge_sysclk

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T7,T12,T1

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T12,T1
1	1	Covered	T7,T12,T1

---

Branch Coverage for Instance : tb.dut.u_csb_edge_sysclk

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_clk_csb_edge_0

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
48	2	2
49	1	1
52	1	1
53	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_csb_edge_0

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T6,T1

---

Branch Coverage for Instance : tb.dut.u_clk_csb_edge_0

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_sck_tog_edge

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
48	2	2
49	1	1
52	1	1
53	1	1

---

Cond Coverage for Instance : tb.dut.u_sck_tog_edge

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T6,T1

---

Branch Coverage for Instance : tb.dut.u_sck_tog_edge

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T6,T1

Line Coverage for Instance : tb.dut.u_readcmd.u_addr_latch_pulse

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	1	1
45	1	1
48	2	2
49	1	1
52	1	1
53	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_addr_latch_pulse

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T1
1	0	Covered	T7,T12,T1
1	1	Covered	T4,T5,T6

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T1
1	0	Covered	T7,T12,T1
1	1	Covered	T7,T12,T1

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_addr_latch_pulse

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	48	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T7,T12,T1