Module Definition
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Module : prim_onehot_check
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check 100.00 100.00



Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_reg_we_check


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_onehot_check
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 144 144 100.00
Total Bits 0->1 72 72 100.00
Total Bits 1->0 72 72 100.00

Ports 5 5 100.00
Port Bits 144 144 100.00
Port Bits 0->1 72 72 100.00
Port Bits 1->0 72 72 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T9,T39,T123 Yes T4,T5,T6 INPUT
oh_i[6:0] Yes Yes *T4,*T6,*T7 Yes T4,T6,T7 INPUT
oh_i[8:7] Unreachable Unreachable Unreachable INPUT
oh_i[13:9] Yes Yes *T2,*T10,*T11 Yes T2,T10,T11 INPUT
oh_i[14] Unreachable Unreachable Unreachable INPUT
oh_i[19:15] Yes Yes T7,T1,T8 Yes T7,T1,T8 INPUT
oh_i[23:20] Unreachable Unreachable Unreachable INPUT
oh_i[63:24] Yes Yes *T7,*T12,T1 Yes T7,T12,T1 INPUT
oh_i[64] Unreachable Unreachable Unreachable INPUT
oh_i[65] Yes Yes *T4,*T6,*T1 Yes T4,T6,T1 INPUT
oh_i[66] Unreachable Unreachable Unreachable INPUT
oh_i[75:67] Yes Yes T1,T8,T31 Yes T1,T8,T31 INPUT
oh_i[76] Unreachable Unreachable Unreachable INPUT
oh_i[77] Yes Yes *T4,*T6,*T1 Yes T4,T6,T1 INPUT
oh_i[78] Unreachable Unreachable Unreachable INPUT
addr_i[6:0] Unreachable Unreachable Unreachable INPUT
en_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
err_o Yes Yes T90,T91,T92 Yes T90,T91,T92 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%