Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
144 |
144 |
100.00 |
Total Bits 0->1 |
72 |
72 |
100.00 |
Total Bits 1->0 |
72 |
72 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
144 |
144 |
100.00 |
Port Bits 0->1 |
72 |
72 |
100.00 |
Port Bits 1->0 |
72 |
72 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T9,T39,T123 |
Yes |
T4,T5,T6 |
INPUT |
oh_i[6:0] |
Yes |
Yes |
*T4,*T6,*T7 |
Yes |
T4,T6,T7 |
INPUT |
oh_i[8:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[13:9] |
Yes |
Yes |
*T2,*T10,*T11 |
Yes |
T2,T10,T11 |
INPUT |
oh_i[14] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[19:15] |
Yes |
Yes |
T7,T1,T8 |
Yes |
T7,T1,T8 |
INPUT |
oh_i[23:20] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[63:24] |
Yes |
Yes |
*T7,*T12,T1 |
Yes |
T7,T12,T1 |
INPUT |
oh_i[64] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[65] |
Yes |
Yes |
*T4,*T6,*T1 |
Yes |
T4,T6,T1 |
INPUT |
oh_i[66] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[75:67] |
Yes |
Yes |
T1,T8,T31 |
Yes |
T1,T8,T31 |
INPUT |
oh_i[76] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[77] |
Yes |
Yes |
*T4,*T6,*T1 |
Yes |
T4,T6,T1 |
INPUT |
oh_i[78] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
addr_i[6:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
err_o |
Yes |
Yes |
T90,T91,T92 |
Yes |
T90,T91,T92 |
OUTPUT |
*Tests covering at least one bit in the range