Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_fwmode_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.53	100.00

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T6

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T1
1	0	Unreachable
1	1	Covered	T2,T3,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T8,T9
1	0	Covered	T7,T12,T1

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T6

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T7,T12,T1

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T1,T2
0	0	1	Unreachable
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T1,T2
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	4803	4803	0	0
GntImpliesReady_A	2147483647	21544822	0	0
GntImpliesValid_A	2147483647	21544822	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	21544822	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	0	0	0
ReadyAndValidImplyGrant_A	2147483647	21544822	0	0
ReqAndReadyImplyGrant_A	2147483647	21544822	0	0
ReqImpliesValid_A	2147483647	21544822	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	842	0	2313
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	21544822	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2039259	1940118	0	0
T2	1074635	1074625	0	0
T3	2338	2242	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	58931	58759	0	0
T8	2191282	2154688	0	0
T10	3761	3661	0	0
T11	426262	426260	0	0
T12	162427	162126	0	0
T13	131616	130780	0	0
T14	740608	740606	0	0
T15	0	384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4803	4803	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T10	3	3	0	0
T12	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21544822	0	0
T1	1154810	19572	0	0
T2	1074635	47208	0	0
T3	2338	6	0	0
T7	15995	1024	0	0
T8	2191282	27467	0	0
T9	0	3816	0	0
T10	3761	32	0	0
T11	751313	12660	0	0
T12	56701	1024	0	0
T13	528188	1024	0	0
T14	740608	70636	0	0
T15	1600	21	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T31	537348	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T37	1428	0	0	0
T40	0	533	0	0
T46	0	3	0	0
T47	0	4100	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21544822	0	0
T1	1154810	19572	0	0
T2	1074635	47208	0	0
T3	2338	6	0	0
T7	15995	1024	0	0
T8	2191282	27467	0	0
T9	0	3816	0	0
T10	3761	32	0	0
T11	751313	12660	0	0
T12	56701	1024	0	0
T13	528188	1024	0	0
T14	740608	70636	0	0
T15	1600	21	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T31	537348	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T37	1428	0	0	0
T40	0	533	0	0
T46	0	3	0	0
T47	0	4100	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2039259	1940118	0	0
T2	1074635	1074625	0	0
T3	2338	2242	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	58931	58759	0	0
T8	2191282	2154688	0	0
T10	3761	3661	0	0
T11	426262	426260	0	0
T12	162427	162126	0	0
T13	131616	130780	0	0
T14	740608	740606	0	0
T15	0	384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2039259	1940118	0	0
T2	1074635	1074625	0	0
T3	2338	2242	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	58931	58759	0	0
T8	2191282	2154688	0	0
T10	3761	3661	0	0
T11	426262	426260	0	0
T12	162427	162126	0	0
T13	131616	130780	0	0
T14	740608	740606	0	0
T15	0	384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21544822	0	0
T1	1154810	19572	0	0
T2	1074635	47208	0	0
T3	2338	6	0	0
T7	15995	1024	0	0
T8	2191282	27467	0	0
T9	0	3816	0	0
T10	3761	32	0	0
T11	751313	12660	0	0
T12	56701	1024	0	0
T13	528188	1024	0	0
T14	740608	70636	0	0
T15	1600	21	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T31	537348	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T37	1428	0	0	0
T40	0	533	0	0
T46	0	3	0	0
T47	0	4100	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21544822	0	0
T1	1154810	19572	0	0
T2	1074635	47208	0	0
T3	2338	6	0	0
T7	15995	1024	0	0
T8	2191282	27467	0	0
T9	0	3816	0	0
T10	3761	32	0	0
T11	751313	12660	0	0
T12	56701	1024	0	0
T13	528188	1024	0	0
T14	740608	70636	0	0
T15	1600	21	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T31	537348	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T37	1428	0	0	0
T40	0	533	0	0
T46	0	3	0	0
T47	0	4100	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21544822	0	0
T1	1154810	19572	0	0
T2	1074635	47208	0	0
T3	2338	6	0	0
T7	15995	1024	0	0
T8	2191282	27467	0	0
T9	0	3816	0	0
T10	3761	32	0	0
T11	751313	12660	0	0
T12	56701	1024	0	0
T13	528188	1024	0	0
T14	740608	70636	0	0
T15	1600	21	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T31	537348	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T37	1428	0	0	0
T40	0	533	0	0
T46	0	3	0	0
T47	0	4100	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21544822	0	0
T1	1154810	19572	0	0
T2	1074635	47208	0	0
T3	2338	6	0	0
T7	15995	1024	0	0
T8	2191282	27467	0	0
T9	0	3816	0	0
T10	3761	32	0	0
T11	751313	12660	0	0
T12	56701	1024	0	0
T13	528188	1024	0	0
T14	740608	70636	0	0
T15	1600	21	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T31	537348	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T37	1428	0	0	0
T40	0	533	0	0
T46	0	3	0	0
T47	0	4100	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	842	0	2313
T9	172804	99	0	0
T18	0	0	0	0
T20	38431	0	0	0
T21	135921	0	0	0
T23	0	0	0	0
T39	326748	0	0	0
T48	131880	1	0	1
T49	376952	3	0	1
T50	0	6	0	1
T51	0	14	0	0
T52	0	31	0	0
T53	0	2	0	0
T54	0	9	0	0
T55	0	4	0	0
T56	0	23	0	0
T57	122266	0	0	1
T58	93273	0	0	1
T59	13388	0	0	1
T60	307319	0	0	1
T61	0	0	0	0
T62	0	0	0	0
T63	0	0	0	1
T64	0	0	0	1
T65	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2039259	1940118	0	0
T2	1074635	1074625	0	0
T3	2338	2242	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	58931	58759	0	0
T8	2191282	2154688	0	0
T10	3761	3661	0	0
T11	426262	426260	0	0
T12	162427	162126	0	0
T13	131616	130780	0	0
T14	740608	740606	0	0
T15	0	384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21544822	0	0
T1	1154810	19572	0	0
T2	1074635	47208	0	0
T3	2338	6	0	0
T7	15995	1024	0	0
T8	2191282	27467	0	0
T9	0	3816	0	0
T10	3761	32	0	0
T11	751313	12660	0	0
T12	56701	1024	0	0
T13	528188	1024	0	0
T14	740608	70636	0	0
T15	1600	21	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T31	537348	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T37	1428	0	0	0
T40	0	533	0	0
T46	0	3	0	0
T47	0	4100	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T6

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T1
1	0	Unreachable
1	1	Covered	T1,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T8,T9
0	0	1	Unreachable
0	0	0	Covered	T7,T12,T1

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	394100318	342026219	0	0
CheckNGreaterZero_A	1601	1601	0	0
GntImpliesReady_A	394100318	569449	0	0
GntImpliesValid_A	394100318	569449	0	0
GrantKnown_A	394100318	342026219	0	0
IdxKnown_A	394100318	342026219	0	0
IndexIsCorrect_A	394100318	569449	0	0
LockArbDecision_A	394100318	0	0	0
NoReadyValidNoGrant_A	394100318	0	0	0
ReadyAndValidImplyGrant_A	394100318	569449	0	0
ReqAndReadyImplyGrant_A	394100318	569449	0	0
ReqImpliesValid_A	394100318	569449	0	0
ReqStaysHighUntilGranted0_M	394100318	0	0	0
RoundRobin_A	394100318	0	0	0
ValidKnown_A	394100318	342026219	0	0
gen_data_port_assertion.DataFlow_A	394100318	569449	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	342026219	0	0
T1	884449	834882	0	0
T2	377666	377664	0	0
T3	1	0	0	0
T7	21468	21422	0	0
T8	836914	818621	0	0
T10	385	384	0	0
T11	101282	101280	0	0
T12	52863	52744	0	0
T13	65808	65390	0	0
T14	565090	565088	0	0
T15	0	384	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	569449	0	0
T1	884449	4878	0	0
T2	377666	0	0	0
T3	1	0	0	0
T8	836914	6511	0	0
T9	0	3816	0	0
T10	385	0	0	0
T11	101282	0	0	0
T13	65808	0	0	0
T14	565090	0	0	0
T15	385	0	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T25	0	8072	0	0
T31	268674	0	0	0
T40	0	533	0	0
T47	0	4100	0	0
T66	0	2115	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	569449	0	0
T1	884449	4878	0	0
T2	377666	0	0	0
T3	1	0	0	0
T8	836914	6511	0	0
T9	0	3816	0	0
T10	385	0	0	0
T11	101282	0	0	0
T13	65808	0	0	0
T14	565090	0	0	0
T15	385	0	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T25	0	8072	0	0
T31	268674	0	0	0
T40	0	533	0	0
T47	0	4100	0	0
T66	0	2115	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	342026219	0	0
T1	884449	834882	0	0
T2	377666	377664	0	0
T3	1	0	0	0
T7	21468	21422	0	0
T8	836914	818621	0	0
T10	385	384	0	0
T11	101282	101280	0	0
T12	52863	52744	0	0
T13	65808	65390	0	0
T14	565090	565088	0	0
T15	0	384	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	342026219	0	0
T1	884449	834882	0	0
T2	377666	377664	0	0
T3	1	0	0	0
T7	21468	21422	0	0
T8	836914	818621	0	0
T10	385	384	0	0
T11	101282	101280	0	0
T12	52863	52744	0	0
T13	65808	65390	0	0
T14	565090	565088	0	0
T15	0	384	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	569449	0	0
T1	884449	4878	0	0
T2	377666	0	0	0
T3	1	0	0	0
T8	836914	6511	0	0
T9	0	3816	0	0
T10	385	0	0	0
T11	101282	0	0	0
T13	65808	0	0	0
T14	565090	0	0	0
T15	385	0	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T25	0	8072	0	0
T31	268674	0	0	0
T40	0	533	0	0
T47	0	4100	0	0
T66	0	2115	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	569449	0	0
T1	884449	4878	0	0
T2	377666	0	0	0
T3	1	0	0	0
T8	836914	6511	0	0
T9	0	3816	0	0
T10	385	0	0	0
T11	101282	0	0	0
T13	65808	0	0	0
T14	565090	0	0	0
T15	385	0	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T25	0	8072	0	0
T31	268674	0	0	0
T40	0	533	0	0
T47	0	4100	0	0
T66	0	2115	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	569449	0	0
T1	884449	4878	0	0
T2	377666	0	0	0
T3	1	0	0	0
T8	836914	6511	0	0
T9	0	3816	0	0
T10	385	0	0	0
T11	101282	0	0	0
T13	65808	0	0	0
T14	565090	0	0	0
T15	385	0	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T25	0	8072	0	0
T31	268674	0	0	0
T40	0	533	0	0
T47	0	4100	0	0
T66	0	2115	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	569449	0	0
T1	884449	4878	0	0
T2	377666	0	0	0
T3	1	0	0	0
T8	836914	6511	0	0
T9	0	3816	0	0
T10	385	0	0	0
T11	101282	0	0	0
T13	65808	0	0	0
T14	565090	0	0	0
T15	385	0	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T25	0	8072	0	0
T31	268674	0	0	0
T40	0	533	0	0
T47	0	4100	0	0
T66	0	2115	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	342026219	0	0
T1	884449	834882	0	0
T2	377666	377664	0	0
T3	1	0	0	0
T7	21468	21422	0	0
T8	836914	818621	0	0
T10	385	384	0	0
T11	101282	101280	0	0
T12	52863	52744	0	0
T13	65808	65390	0	0
T14	565090	565088	0	0
T15	0	384	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394100318	569449	0	0
T1	884449	4878	0	0
T2	377666	0	0	0
T3	1	0	0	0
T8	836914	6511	0	0
T9	0	3816	0	0
T10	385	0	0	0
T11	101282	0	0	0
T13	65808	0	0	0
T14	565090	0	0	0
T15	385	0	0	0
T18	0	4	0	0
T19	0	1402	0	0
T24	0	3049	0	0
T25	0	8072	0	0
T31	268674	0	0	0
T40	0	533	0	0
T47	0	4100	0	0
T66	0	2115	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T8,T9
1	0	Covered	T7,T12,T1

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T6

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T7,T12,T1

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T12,T1
0	0	1	Unreachable
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T1
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2049979927	2049845846	0	0
CheckNGreaterZero_A	1601	1601	0	0
GntImpliesReady_A	2049979927	11689266	0	0
GntImpliesValid_A	2049979927	11689266	0	0
GrantKnown_A	2049979927	2049845846	0	0
IdxKnown_A	2049979927	2049845846	0	0
IndexIsCorrect_A	2049979927	11689266	0	0
LockArbDecision_A	2049979927	0	0	0
NoReadyValidNoGrant_A	2049979927	0	0	0
ReadyAndValidImplyGrant_A	2049979927	11689266	0	0
ReqAndReadyImplyGrant_A	2049979927	11689266	0	0
ReqImpliesValid_A	2049979927	11689266	0	0
ReqStaysHighUntilGranted0_M	2049979927	0	0	0
RoundRobin_A	2049979927	0	0	1601
ValidKnown_A	2049979927	2049845846	0	0
gen_data_port_assertion.DataFlow_A	2049979927	11689266	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	2049845846	0	0
T1	270361	270354	0	0
T2	348489	348481	0	0
T3	1222	1127	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	15995	15915	0	0
T8	517454	517446	0	0
T10	1745	1646	0	0
T12	56701	56638	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	11689266	0	0
T1	270361	14694	0	0
T2	348489	23604	0	0
T3	1222	4	0	0
T7	15995	1024	0	0
T8	517454	20956	0	0
T10	1745	12	0	0
T11	325051	6330	0	0
T12	56701	1024	0	0
T13	396572	1024	0	0
T14	0	35318	0	0
T37	1428	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	11689266	0	0
T1	270361	14694	0	0
T2	348489	23604	0	0
T3	1222	4	0	0
T7	15995	1024	0	0
T8	517454	20956	0	0
T10	1745	12	0	0
T11	325051	6330	0	0
T12	56701	1024	0	0
T13	396572	1024	0	0
T14	0	35318	0	0
T37	1428	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	2049845846	0	0
T1	270361	270354	0	0
T2	348489	348481	0	0
T3	1222	1127	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	15995	15915	0	0
T8	517454	517446	0	0
T10	1745	1646	0	0
T12	56701	56638	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	2049845846	0	0
T1	270361	270354	0	0
T2	348489	348481	0	0
T3	1222	1127	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	15995	15915	0	0
T8	517454	517446	0	0
T10	1745	1646	0	0
T12	56701	56638	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	11689266	0	0
T1	270361	14694	0	0
T2	348489	23604	0	0
T3	1222	4	0	0
T7	15995	1024	0	0
T8	517454	20956	0	0
T10	1745	12	0	0
T11	325051	6330	0	0
T12	56701	1024	0	0
T13	396572	1024	0	0
T14	0	35318	0	0
T37	1428	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	11689266	0	0
T1	270361	14694	0	0
T2	348489	23604	0	0
T3	1222	4	0	0
T7	15995	1024	0	0
T8	517454	20956	0	0
T10	1745	12	0	0
T11	325051	6330	0	0
T12	56701	1024	0	0
T13	396572	1024	0	0
T14	0	35318	0	0
T37	1428	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	11689266	0	0
T1	270361	14694	0	0
T2	348489	23604	0	0
T3	1222	4	0	0
T7	15995	1024	0	0
T8	517454	20956	0	0
T10	1745	12	0	0
T11	325051	6330	0	0
T12	56701	1024	0	0
T13	396572	1024	0	0
T14	0	35318	0	0
T37	1428	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	11689266	0	0
T1	270361	14694	0	0
T2	348489	23604	0	0
T3	1222	4	0	0
T7	15995	1024	0	0
T8	517454	20956	0	0
T10	1745	12	0	0
T11	325051	6330	0	0
T12	56701	1024	0	0
T13	396572	1024	0	0
T14	0	35318	0	0
T37	1428	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	0	0	1601

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	2049845846	0	0
T1	270361	270354	0	0
T2	348489	348481	0	0
T3	1222	1127	0	0
T4	3172	3108	0	0
T5	1149	1078	0	0
T6	15012	14961	0	0
T7	15995	15915	0	0
T8	517454	517446	0	0
T10	1745	1646	0	0
T12	56701	56638	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2049979927	11689266	0	0
T1	270361	14694	0	0
T2	348489	23604	0	0
T3	1222	4	0	0
T7	15995	1024	0	0
T8	517454	20956	0	0
T10	1745	12	0	0
T11	325051	6330	0	0
T12	56701	1024	0	0
T13	396572	1024	0	0
T14	0	35318	0	0
T37	1428	0	0	0

Line Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T4,T5,T6

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T12,T1
1	0	Unreachable
1	1	Covered	T2,T3,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T2,T3,T10
0	0	1	Unreachable
0	0	0	Covered	T7,T12,T1

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1682880266	1645751674	0	0
CheckNGreaterZero_A	1601	1601	0	0
GntImpliesReady_A	1682880266	9286107	0	0
GntImpliesValid_A	1682880266	9286107	0	0
GrantKnown_A	1682880266	1645751674	0	0
IdxKnown_A	1682880266	1645751674	0	0
IndexIsCorrect_A	1682880266	9286107	0	0
LockArbDecision_A	1682880266	0	0	0
NoReadyValidNoGrant_A	1682880266	0	0	0
ReadyAndValidImplyGrant_A	1682880266	9286107	0	0
ReqAndReadyImplyGrant_A	1682880266	9286107	0	0
ReqImpliesValid_A	1682880266	9286107	0	0
ReqStaysHighUntilGranted0_M	1682880266	0	0	0
RoundRobin_A	1682880266	842	0	712
ValidKnown_A	1682880266	1645751674	0	0
gen_data_port_assertion.DataFlow_A	1682880266	9286107	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	1645751674	0	0
T1	884449	834882	0	0
T2	348480	348480	0	0
T3	1115	1115	0	0
T7	21468	21422	0	0
T8	836914	818621	0	0
T10	1631	1631	0	0
T11	324980	324980	0	0
T12	52863	52744	0	0
T13	65808	65390	0	0
T14	175518	175518	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1601	1601	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	9286107	0	0
T2	348480	23604	0	0
T3	1115	2	0	0
T8	836914	0	0	0
T10	1631	20	0	0
T11	324980	6330	0	0
T13	65808	0	0	0
T14	175518	35318	0	0
T15	1215	21	0	0
T31	268674	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T46	0	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	9286107	0	0
T2	348480	23604	0	0
T3	1115	2	0	0
T8	836914	0	0	0
T10	1631	20	0	0
T11	324980	6330	0	0
T13	65808	0	0	0
T14	175518	35318	0	0
T15	1215	21	0	0
T31	268674	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T46	0	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	1645751674	0	0
T1	884449	834882	0	0
T2	348480	348480	0	0
T3	1115	1115	0	0
T7	21468	21422	0	0
T8	836914	818621	0	0
T10	1631	1631	0	0
T11	324980	324980	0	0
T12	52863	52744	0	0
T13	65808	65390	0	0
T14	175518	175518	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	1645751674	0	0
T1	884449	834882	0	0
T2	348480	348480	0	0
T3	1115	1115	0	0
T7	21468	21422	0	0
T8	836914	818621	0	0
T10	1631	1631	0	0
T11	324980	324980	0	0
T12	52863	52744	0	0
T13	65808	65390	0	0
T14	175518	175518	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	9286107	0	0
T2	348480	23604	0	0
T3	1115	2	0	0
T8	836914	0	0	0
T10	1631	20	0	0
T11	324980	6330	0	0
T13	65808	0	0	0
T14	175518	35318	0	0
T15	1215	21	0	0
T31	268674	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T46	0	3	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	9286107	0	0
T2	348480	23604	0	0
T3	1115	2	0	0
T8	836914	0	0	0
T10	1631	20	0	0
T11	324980	6330	0	0
T13	65808	0	0	0
T14	175518	35318	0	0
T15	1215	21	0	0
T31	268674	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T46	0	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	9286107	0	0
T2	348480	23604	0	0
T3	1115	2	0	0
T8	836914	0	0	0
T10	1631	20	0	0
T11	324980	6330	0	0
T13	65808	0	0	0
T14	175518	35318	0	0
T15	1215	21	0	0
T31	268674	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T46	0	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	9286107	0	0
T2	348480	23604	0	0
T3	1115	2	0	0
T8	836914	0	0	0
T10	1631	20	0	0
T11	324980	6330	0	0
T13	65808	0	0	0
T14	175518	35318	0	0
T15	1215	21	0	0
T31	268674	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T46	0	3	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	842	0	712
T9	172804	99	0	0
T18	0	0	0	0
T20	38431	0	0	0
T21	135921	0	0	0
T23	0	0	0	0
T39	326748	0	0	0
T48	131880	1	0	1
T49	376952	3	0	1
T50	0	6	0	1
T51	0	14	0	0
T52	0	31	0	0
T53	0	2	0	0
T54	0	9	0	0
T55	0	4	0	0
T56	0	23	0	0
T57	122266	0	0	1
T58	93273	0	0	1
T59	13388	0	0	1
T60	307319	0	0	1
T61	0	0	0	0
T62	0	0	0	0
T63	0	0	0	1
T64	0	0	0	1
T65	0	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	1645751674	0	0
T1	884449	834882	0	0
T2	348480	348480	0	0
T3	1115	1115	0	0
T7	21468	21422	0	0
T8	836914	818621	0	0
T10	1631	1631	0	0
T11	324980	324980	0	0
T12	52863	52744	0	0
T13	65808	65390	0	0
T14	175518	175518	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1682880266	9286107	0	0
T2	348480	23604	0	0
T3	1115	2	0	0
T8	836914	0	0	0
T10	1631	20	0	0
T11	324980	6330	0	0
T13	65808	0	0	0
T14	175518	35318	0	0
T15	1215	21	0	0
T31	268674	0	0	0
T32	0	31936	0	0
T33	0	20878	0	0
T34	0	24964	0	0
T36	113230	0	0	0
T46	0	3	0	0