Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
8197 |
0 |
0 |
T84 |
54931 |
2 |
0 |
0 |
T85 |
91933 |
7 |
0 |
0 |
T86 |
18633 |
691 |
0 |
0 |
T115 |
8408 |
279 |
0 |
0 |
T116 |
2546 |
242 |
0 |
0 |
T117 |
73330 |
4 |
0 |
0 |
T120 |
0 |
608 |
0 |
0 |
T133 |
0 |
1 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
0 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
1838 |
0 |
0 |
T85 |
91933 |
41 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
70 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
2 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
11 |
0 |
0 |
T154 |
0 |
11 |
0 |
0 |
T155 |
0 |
447 |
0 |
0 |
T157 |
0 |
432 |
0 |
0 |
T160 |
0 |
5 |
0 |
0 |
T171 |
0 |
1 |
0 |
0 |
T172 |
0 |
15 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
1884 |
0 |
0 |
T85 |
91933 |
72 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
77 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
14 |
0 |
0 |
T150 |
0 |
15 |
0 |
0 |
T154 |
0 |
11 |
0 |
0 |
T155 |
0 |
401 |
0 |
0 |
T157 |
0 |
464 |
0 |
0 |
T160 |
0 |
3 |
0 |
0 |
T172 |
0 |
9 |
0 |
0 |
T173 |
2325 |
2 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
8689 |
0 |
0 |
T85 |
91933 |
1101 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
1160 |
0 |
0 |
T121 |
0 |
9 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
9 |
0 |
0 |
T150 |
0 |
11 |
0 |
0 |
T154 |
0 |
142 |
0 |
0 |
T155 |
0 |
457 |
0 |
0 |
T157 |
0 |
490 |
0 |
0 |
T160 |
0 |
4 |
0 |
0 |
T173 |
2325 |
3 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
8140 |
0 |
0 |
T85 |
91933 |
1063 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
1409 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
20 |
0 |
0 |
T150 |
0 |
10 |
0 |
0 |
T154 |
0 |
6 |
0 |
0 |
T155 |
0 |
477 |
0 |
0 |
T157 |
0 |
436 |
0 |
0 |
T160 |
0 |
1 |
0 |
0 |
T172 |
0 |
4 |
0 |
0 |
T173 |
2325 |
8 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
9318 |
0 |
0 |
T85 |
91933 |
1160 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
1798 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
41 |
0 |
0 |
T150 |
0 |
8 |
0 |
0 |
T154 |
0 |
88 |
0 |
0 |
T155 |
0 |
483 |
0 |
0 |
T157 |
0 |
395 |
0 |
0 |
T160 |
0 |
5 |
0 |
0 |
T172 |
0 |
4 |
0 |
0 |
T173 |
2325 |
6 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
7867 |
0 |
0 |
T85 |
91933 |
783 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
1410 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
11 |
0 |
0 |
T150 |
0 |
7 |
0 |
0 |
T154 |
0 |
105 |
0 |
0 |
T155 |
0 |
423 |
0 |
0 |
T157 |
0 |
426 |
0 |
0 |
T171 |
0 |
1 |
0 |
0 |
T172 |
0 |
6 |
0 |
0 |
T173 |
2325 |
5 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
9008 |
0 |
0 |
T85 |
91933 |
1265 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
1564 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
32 |
0 |
0 |
T150 |
0 |
7 |
0 |
0 |
T154 |
0 |
163 |
0 |
0 |
T155 |
0 |
445 |
0 |
0 |
T157 |
0 |
457 |
0 |
0 |
T160 |
0 |
2 |
0 |
0 |
T172 |
0 |
6 |
0 |
0 |
T173 |
2325 |
5 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
6923 |
0 |
0 |
T85 |
91933 |
996 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
968 |
0 |
0 |
T119 |
0 |
2 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
6 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T154 |
0 |
111 |
0 |
0 |
T155 |
0 |
453 |
0 |
0 |
T157 |
0 |
438 |
0 |
0 |
T171 |
0 |
3 |
0 |
0 |
T173 |
2325 |
2 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
8946 |
0 |
0 |
T85 |
91933 |
1143 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
1141 |
0 |
0 |
T119 |
0 |
4 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
9 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
11 |
0 |
0 |
T154 |
0 |
222 |
0 |
0 |
T155 |
0 |
433 |
0 |
0 |
T157 |
0 |
437 |
0 |
0 |
T160 |
0 |
4 |
0 |
0 |
T172 |
0 |
4 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
8614 |
0 |
0 |
T85 |
91933 |
682 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
1485 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
7 |
0 |
0 |
T150 |
0 |
12 |
0 |
0 |
T154 |
0 |
232 |
0 |
0 |
T155 |
0 |
413 |
0 |
0 |
T157 |
0 |
473 |
0 |
0 |
T171 |
0 |
8 |
0 |
0 |
T172 |
0 |
6 |
0 |
0 |
T173 |
2325 |
6 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4155 |
0 |
0 |
T85 |
91933 |
423 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
481 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
30 |
0 |
0 |
T150 |
0 |
13 |
0 |
0 |
T154 |
0 |
16 |
0 |
0 |
T155 |
0 |
425 |
0 |
0 |
T157 |
0 |
465 |
0 |
0 |
T160 |
0 |
3 |
0 |
0 |
T172 |
0 |
10 |
0 |
0 |
T173 |
2325 |
2 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
3609 |
0 |
0 |
T85 |
91933 |
350 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
487 |
0 |
0 |
T119 |
0 |
10 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
18 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
10 |
0 |
0 |
T154 |
0 |
82 |
0 |
0 |
T155 |
0 |
480 |
0 |
0 |
T157 |
0 |
423 |
0 |
0 |
T160 |
0 |
6 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4063 |
0 |
0 |
T85 |
91933 |
420 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
402 |
0 |
0 |
T119 |
0 |
4 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
15 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
11 |
0 |
0 |
T154 |
0 |
7 |
0 |
0 |
T155 |
0 |
472 |
0 |
0 |
T157 |
0 |
456 |
0 |
0 |
T160 |
0 |
2 |
0 |
0 |
T171 |
0 |
3 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
3776 |
0 |
0 |
T85 |
91933 |
383 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
356 |
0 |
0 |
T119 |
0 |
4 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
30 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
9 |
0 |
0 |
T154 |
0 |
39 |
0 |
0 |
T155 |
0 |
459 |
0 |
0 |
T157 |
0 |
444 |
0 |
0 |
T160 |
0 |
7 |
0 |
0 |
T172 |
0 |
9 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4429 |
0 |
0 |
T85 |
91933 |
352 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
503 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
11 |
0 |
0 |
T150 |
0 |
10 |
0 |
0 |
T154 |
0 |
9 |
0 |
0 |
T155 |
0 |
448 |
0 |
0 |
T157 |
0 |
516 |
0 |
0 |
T160 |
0 |
2 |
0 |
0 |
T171 |
0 |
3 |
0 |
0 |
T173 |
2325 |
4 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4343 |
0 |
0 |
T85 |
91933 |
349 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
612 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
48 |
0 |
0 |
T150 |
0 |
5 |
0 |
0 |
T154 |
0 |
50 |
0 |
0 |
T155 |
0 |
410 |
0 |
0 |
T157 |
0 |
444 |
0 |
0 |
T160 |
0 |
7 |
0 |
0 |
T172 |
0 |
10 |
0 |
0 |
T173 |
2325 |
8 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4639 |
0 |
0 |
T85 |
91933 |
345 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
624 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
8 |
0 |
0 |
T150 |
0 |
10 |
0 |
0 |
T154 |
0 |
98 |
0 |
0 |
T155 |
0 |
518 |
0 |
0 |
T157 |
0 |
413 |
0 |
0 |
T160 |
0 |
3 |
0 |
0 |
T172 |
0 |
8 |
0 |
0 |
T173 |
2325 |
1 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
3763 |
0 |
0 |
T85 |
91933 |
479 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
316 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
20 |
0 |
0 |
T150 |
0 |
9 |
0 |
0 |
T154 |
0 |
92 |
0 |
0 |
T155 |
0 |
460 |
0 |
0 |
T157 |
0 |
503 |
0 |
0 |
T160 |
0 |
2 |
0 |
0 |
T172 |
0 |
7 |
0 |
0 |
T173 |
2325 |
3 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
3832 |
0 |
0 |
T85 |
91933 |
351 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
271 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
42 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
9 |
0 |
0 |
T154 |
0 |
31 |
0 |
0 |
T155 |
0 |
457 |
0 |
0 |
T157 |
0 |
457 |
0 |
0 |
T160 |
0 |
6 |
0 |
0 |
T171 |
0 |
5 |
0 |
0 |
T172 |
0 |
5 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
3920 |
0 |
0 |
T85 |
91933 |
324 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
418 |
0 |
0 |
T119 |
0 |
2 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
18 |
0 |
0 |
T150 |
0 |
5 |
0 |
0 |
T154 |
0 |
36 |
0 |
0 |
T155 |
0 |
376 |
0 |
0 |
T157 |
0 |
511 |
0 |
0 |
T160 |
0 |
4 |
0 |
0 |
T173 |
2325 |
2 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4105 |
0 |
0 |
T85 |
91933 |
331 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
443 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
22 |
0 |
0 |
T150 |
0 |
9 |
0 |
0 |
T154 |
0 |
28 |
0 |
0 |
T155 |
0 |
448 |
0 |
0 |
T157 |
0 |
393 |
0 |
0 |
T160 |
0 |
3 |
0 |
0 |
T172 |
0 |
11 |
0 |
0 |
T173 |
2325 |
5 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4363 |
0 |
0 |
T85 |
91933 |
417 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
433 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
8 |
0 |
0 |
T150 |
0 |
9 |
0 |
0 |
T154 |
0 |
109 |
0 |
0 |
T155 |
0 |
483 |
0 |
0 |
T157 |
0 |
469 |
0 |
0 |
T160 |
0 |
7 |
0 |
0 |
T172 |
0 |
12 |
0 |
0 |
T173 |
2325 |
2 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4341 |
0 |
0 |
T85 |
91933 |
356 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
561 |
0 |
0 |
T119 |
0 |
4 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
19 |
0 |
0 |
T150 |
0 |
12 |
0 |
0 |
T154 |
0 |
58 |
0 |
0 |
T155 |
0 |
449 |
0 |
0 |
T157 |
0 |
474 |
0 |
0 |
T160 |
0 |
7 |
0 |
0 |
T173 |
2325 |
3 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4321 |
0 |
0 |
T85 |
91933 |
357 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
682 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
28 |
0 |
0 |
T150 |
0 |
8 |
0 |
0 |
T154 |
0 |
4 |
0 |
0 |
T155 |
0 |
422 |
0 |
0 |
T157 |
0 |
482 |
0 |
0 |
T160 |
0 |
2 |
0 |
0 |
T172 |
0 |
5 |
0 |
0 |
T173 |
2325 |
1 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4164 |
0 |
0 |
T85 |
91933 |
453 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
461 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
6 |
0 |
0 |
T150 |
0 |
8 |
0 |
0 |
T154 |
0 |
15 |
0 |
0 |
T155 |
0 |
468 |
0 |
0 |
T157 |
0 |
415 |
0 |
0 |
T160 |
0 |
7 |
0 |
0 |
T171 |
0 |
4 |
0 |
0 |
T173 |
2325 |
9 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4225 |
0 |
0 |
T85 |
91933 |
374 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
401 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
38 |
0 |
0 |
T150 |
0 |
16 |
0 |
0 |
T154 |
0 |
86 |
0 |
0 |
T155 |
0 |
475 |
0 |
0 |
T157 |
0 |
435 |
0 |
0 |
T160 |
0 |
1 |
0 |
0 |
T171 |
0 |
8 |
0 |
0 |
T173 |
2325 |
5 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4466 |
0 |
0 |
T85 |
91933 |
361 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
682 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
23 |
0 |
0 |
T150 |
0 |
16 |
0 |
0 |
T154 |
0 |
9 |
0 |
0 |
T155 |
0 |
438 |
0 |
0 |
T157 |
0 |
494 |
0 |
0 |
T171 |
0 |
5 |
0 |
0 |
T172 |
0 |
10 |
0 |
0 |
T173 |
2325 |
10 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4266 |
0 |
0 |
T85 |
91933 |
344 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
453 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
21 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T154 |
0 |
59 |
0 |
0 |
T155 |
0 |
451 |
0 |
0 |
T157 |
0 |
487 |
0 |
0 |
T160 |
0 |
1 |
0 |
0 |
T171 |
0 |
3 |
0 |
0 |
T173 |
2325 |
5 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4238 |
0 |
0 |
T85 |
91933 |
430 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
499 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
45 |
0 |
0 |
T150 |
0 |
10 |
0 |
0 |
T154 |
0 |
10 |
0 |
0 |
T155 |
0 |
451 |
0 |
0 |
T157 |
0 |
502 |
0 |
0 |
T160 |
0 |
2 |
0 |
0 |
T171 |
0 |
2 |
0 |
0 |
T173 |
2325 |
1 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4387 |
0 |
0 |
T85 |
91933 |
631 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
373 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
3 |
0 |
0 |
T150 |
0 |
6 |
0 |
0 |
T154 |
0 |
82 |
0 |
0 |
T155 |
0 |
462 |
0 |
0 |
T157 |
0 |
438 |
0 |
0 |
T160 |
0 |
4 |
0 |
0 |
T172 |
0 |
8 |
0 |
0 |
T173 |
2325 |
1 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4198 |
0 |
0 |
T85 |
91933 |
387 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
496 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
20 |
0 |
0 |
T150 |
0 |
7 |
0 |
0 |
T154 |
0 |
101 |
0 |
0 |
T155 |
0 |
465 |
0 |
0 |
T157 |
0 |
456 |
0 |
0 |
T160 |
0 |
1 |
0 |
0 |
T172 |
0 |
8 |
0 |
0 |
T173 |
2325 |
3 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4097 |
0 |
0 |
T85 |
91933 |
382 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
476 |
0 |
0 |
T120 |
0 |
7 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
36 |
0 |
0 |
T150 |
0 |
8 |
0 |
0 |
T154 |
0 |
54 |
0 |
0 |
T155 |
0 |
392 |
0 |
0 |
T157 |
0 |
467 |
0 |
0 |
T171 |
0 |
7 |
0 |
0 |
T173 |
2325 |
9 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
3772 |
0 |
0 |
T85 |
91933 |
463 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
209 |
0 |
0 |
T119 |
0 |
1 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
23 |
0 |
0 |
T150 |
0 |
8 |
0 |
0 |
T154 |
0 |
41 |
0 |
0 |
T155 |
0 |
438 |
0 |
0 |
T157 |
0 |
454 |
0 |
0 |
T160 |
0 |
1 |
0 |
0 |
T173 |
2325 |
2 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4226 |
0 |
0 |
T85 |
91933 |
415 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
473 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
10 |
0 |
0 |
T150 |
0 |
14 |
0 |
0 |
T154 |
0 |
61 |
0 |
0 |
T155 |
0 |
415 |
0 |
0 |
T157 |
0 |
476 |
0 |
0 |
T160 |
0 |
3 |
0 |
0 |
T173 |
2325 |
1 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
T175 |
0 |
6 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2086 |
0 |
0 |
T85 |
91933 |
77 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
121 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
36 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
6 |
0 |
0 |
T154 |
0 |
16 |
0 |
0 |
T155 |
0 |
442 |
0 |
0 |
T157 |
0 |
366 |
0 |
0 |
T171 |
0 |
5 |
0 |
0 |
T172 |
0 |
15 |
0 |
0 |
T175 |
0 |
1 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2124 |
0 |
0 |
T85 |
91933 |
90 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
97 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
2 |
0 |
0 |
T150 |
0 |
5 |
0 |
0 |
T154 |
0 |
11 |
0 |
0 |
T155 |
0 |
424 |
0 |
0 |
T157 |
0 |
418 |
0 |
0 |
T160 |
0 |
7 |
0 |
0 |
T172 |
0 |
7 |
0 |
0 |
T173 |
2325 |
9 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2202 |
0 |
0 |
T85 |
91933 |
89 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
128 |
0 |
0 |
T120 |
0 |
9 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
6 |
0 |
0 |
T154 |
0 |
6 |
0 |
0 |
T155 |
0 |
460 |
0 |
0 |
T157 |
0 |
476 |
0 |
0 |
T160 |
0 |
8 |
0 |
0 |
T173 |
2325 |
3 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
T175 |
0 |
13 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2186 |
0 |
0 |
T85 |
91933 |
82 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
94 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
10 |
0 |
0 |
T150 |
0 |
15 |
0 |
0 |
T154 |
0 |
16 |
0 |
0 |
T155 |
0 |
499 |
0 |
0 |
T157 |
0 |
431 |
0 |
0 |
T160 |
0 |
9 |
0 |
0 |
T172 |
0 |
12 |
0 |
0 |
T173 |
2325 |
3 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
control_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2861 |
0 |
0 |
T85 |
91933 |
190 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
190 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
10 |
0 |
0 |
T150 |
0 |
5 |
0 |
0 |
T154 |
0 |
30 |
0 |
0 |
T155 |
0 |
474 |
0 |
0 |
T157 |
0 |
403 |
0 |
0 |
T160 |
0 |
2 |
0 |
0 |
T171 |
0 |
5 |
0 |
0 |
T173 |
2325 |
10 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
fifo_level_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2045 |
0 |
0 |
T85 |
91933 |
106 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
97 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
11 |
0 |
0 |
T150 |
0 |
6 |
0 |
0 |
T154 |
0 |
11 |
0 |
0 |
T155 |
0 |
431 |
0 |
0 |
T157 |
0 |
419 |
0 |
0 |
T160 |
0 |
4 |
0 |
0 |
T172 |
0 |
3 |
0 |
0 |
T173 |
2325 |
7 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2374 |
0 |
0 |
T85 |
91933 |
126 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
111 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
3 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
7 |
0 |
0 |
T154 |
0 |
17 |
0 |
0 |
T155 |
0 |
477 |
0 |
0 |
T157 |
0 |
450 |
0 |
0 |
T160 |
0 |
1 |
0 |
0 |
T171 |
0 |
2 |
0 |
0 |
T172 |
0 |
5 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
4452 |
0 |
0 |
T69 |
1497 |
33 |
0 |
0 |
T85 |
91933 |
276 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T117 |
73330 |
614 |
0 |
0 |
T134 |
1581 |
22 |
0 |
0 |
T135 |
1312 |
15 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
7 |
0 |
0 |
T150 |
0 |
6 |
0 |
0 |
T171 |
0 |
5 |
0 |
0 |
T173 |
2325 |
9 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
T176 |
0 |
32 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2099 |
0 |
0 |
T85 |
91933 |
99 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
80 |
0 |
0 |
T119 |
0 |
2 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
11 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
16 |
0 |
0 |
T154 |
0 |
11 |
0 |
0 |
T155 |
0 |
468 |
0 |
0 |
T157 |
0 |
470 |
0 |
0 |
T171 |
0 |
8 |
0 |
0 |
T172 |
0 |
7 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2185 |
0 |
0 |
T85 |
91933 |
151 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
127 |
0 |
0 |
T120 |
0 |
7 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
4 |
0 |
0 |
T150 |
0 |
12 |
0 |
0 |
T154 |
0 |
12 |
0 |
0 |
T155 |
0 |
462 |
0 |
0 |
T157 |
0 |
473 |
0 |
0 |
T171 |
0 |
1 |
0 |
0 |
T173 |
2325 |
1 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
1915 |
0 |
0 |
T85 |
91933 |
53 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
79 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
23 |
0 |
0 |
T150 |
0 |
11 |
0 |
0 |
T154 |
0 |
11 |
0 |
0 |
T155 |
0 |
483 |
0 |
0 |
T157 |
0 |
448 |
0 |
0 |
T160 |
0 |
7 |
0 |
0 |
T172 |
0 |
7 |
0 |
0 |
T173 |
2325 |
7 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
1841 |
0 |
0 |
T85 |
91933 |
31 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
74 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
31 |
0 |
0 |
T150 |
0 |
10 |
0 |
0 |
T154 |
0 |
4 |
0 |
0 |
T155 |
0 |
446 |
0 |
0 |
T157 |
0 |
424 |
0 |
0 |
T160 |
0 |
7 |
0 |
0 |
T172 |
0 |
1 |
0 |
0 |
T173 |
2325 |
3 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2006 |
0 |
0 |
T85 |
91933 |
65 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
72 |
0 |
0 |
T120 |
0 |
10 |
0 |
0 |
T121 |
0 |
3 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
29 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
8 |
0 |
0 |
T154 |
0 |
1 |
0 |
0 |
T155 |
0 |
474 |
0 |
0 |
T157 |
0 |
431 |
0 |
0 |
T160 |
0 |
7 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
1937 |
0 |
0 |
T85 |
91933 |
45 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
65 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
28 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
13 |
0 |
0 |
T154 |
0 |
8 |
0 |
0 |
T155 |
0 |
421 |
0 |
0 |
T157 |
0 |
440 |
0 |
0 |
T160 |
0 |
1 |
0 |
0 |
T172 |
0 |
5 |
0 |
0 |
T175 |
0 |
14 |
0 |
0 |
rxf_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2173 |
0 |
0 |
T85 |
91933 |
90 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
96 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
46 |
0 |
0 |
T150 |
0 |
9 |
0 |
0 |
T154 |
0 |
17 |
0 |
0 |
T155 |
0 |
464 |
0 |
0 |
T157 |
0 |
468 |
0 |
0 |
T160 |
0 |
3 |
0 |
0 |
T171 |
0 |
10 |
0 |
0 |
T173 |
2325 |
1 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2539 |
0 |
0 |
T85 |
91933 |
119 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
161 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
33 |
0 |
0 |
T150 |
0 |
8 |
0 |
0 |
T154 |
0 |
38 |
0 |
0 |
T155 |
0 |
453 |
0 |
0 |
T157 |
0 |
464 |
0 |
0 |
T160 |
0 |
1 |
0 |
0 |
T172 |
0 |
1 |
0 |
0 |
T173 |
2325 |
6 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
1910 |
0 |
0 |
T85 |
91933 |
76 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
90 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
8 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
11 |
0 |
0 |
T154 |
0 |
1 |
0 |
0 |
T155 |
0 |
385 |
0 |
0 |
T157 |
0 |
427 |
0 |
0 |
T171 |
0 |
10 |
0 |
0 |
T172 |
0 |
5 |
0 |
0 |
T175 |
0 |
6 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2671 |
0 |
0 |
T85 |
91933 |
130 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
220 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
24 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T154 |
0 |
29 |
0 |
0 |
T155 |
0 |
447 |
0 |
0 |
T157 |
0 |
437 |
0 |
0 |
T160 |
0 |
8 |
0 |
0 |
T172 |
0 |
17 |
0 |
0 |
T173 |
2325 |
2 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2142 |
0 |
0 |
T85 |
91933 |
95 |
0 |
0 |
T115 |
8408 |
8 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
113 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
49 |
0 |
0 |
T150 |
0 |
9 |
0 |
0 |
T154 |
0 |
11 |
0 |
0 |
T155 |
0 |
451 |
0 |
0 |
T157 |
0 |
486 |
0 |
0 |
T171 |
0 |
6 |
0 |
0 |
T173 |
2325 |
9 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
1905 |
0 |
0 |
T85 |
91933 |
74 |
0 |
0 |
T115 |
8408 |
5 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
82 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
23 |
0 |
0 |
T150 |
0 |
5 |
0 |
0 |
T154 |
0 |
8 |
0 |
0 |
T155 |
0 |
412 |
0 |
0 |
T157 |
0 |
467 |
0 |
0 |
T171 |
0 |
2 |
0 |
0 |
T173 |
2325 |
10 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
1860 |
0 |
0 |
T85 |
91933 |
77 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
72 |
0 |
0 |
T121 |
0 |
4 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
26 |
0 |
0 |
T150 |
0 |
9 |
0 |
0 |
T154 |
0 |
1 |
0 |
0 |
T155 |
0 |
418 |
0 |
0 |
T157 |
0 |
389 |
0 |
0 |
T160 |
0 |
7 |
0 |
0 |
T173 |
2325 |
10 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
1961 |
0 |
0 |
T85 |
91933 |
68 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
69 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
8 |
0 |
0 |
T150 |
0 |
10 |
0 |
0 |
T154 |
0 |
10 |
0 |
0 |
T155 |
0 |
470 |
0 |
0 |
T157 |
0 |
401 |
0 |
0 |
T160 |
0 |
7 |
0 |
0 |
T172 |
0 |
3 |
0 |
0 |
T173 |
2325 |
3 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
1875 |
0 |
0 |
T85 |
91933 |
57 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
71 |
0 |
0 |
T133 |
1539 |
0 |
0 |
0 |
T137 |
7641 |
29 |
0 |
0 |
T138 |
13078 |
0 |
0 |
0 |
T145 |
2114 |
0 |
0 |
0 |
T146 |
1733 |
0 |
0 |
0 |
T147 |
3371 |
0 |
0 |
0 |
T148 |
2161 |
0 |
0 |
0 |
T150 |
0 |
6 |
0 |
0 |
T154 |
0 |
13 |
0 |
0 |
T155 |
0 |
447 |
0 |
0 |
T157 |
0 |
375 |
0 |
0 |
T161 |
0 |
258 |
0 |
0 |
T177 |
0 |
4 |
0 |
0 |
T178 |
0 |
1 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
1940 |
0 |
0 |
T85 |
91933 |
59 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
76 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
8 |
0 |
0 |
T150 |
0 |
10 |
0 |
0 |
T154 |
0 |
6 |
0 |
0 |
T155 |
0 |
450 |
0 |
0 |
T157 |
0 |
510 |
0 |
0 |
T160 |
0 |
8 |
0 |
0 |
T172 |
0 |
5 |
0 |
0 |
T173 |
2325 |
1 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
1978 |
0 |
0 |
T85 |
91933 |
42 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
72 |
0 |
0 |
T119 |
0 |
2 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
12 |
0 |
0 |
T150 |
0 |
10 |
0 |
0 |
T154 |
0 |
3 |
0 |
0 |
T155 |
0 |
452 |
0 |
0 |
T157 |
0 |
436 |
0 |
0 |
T171 |
0 |
2 |
0 |
0 |
T173 |
2325 |
2 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |
txf_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2052592437 |
2112 |
0 |
0 |
T85 |
91933 |
79 |
0 |
0 |
T115 |
8408 |
0 |
0 |
0 |
T116 |
2546 |
0 |
0 |
0 |
T117 |
73330 |
129 |
0 |
0 |
T121 |
0 |
6 |
0 |
0 |
T134 |
1581 |
0 |
0 |
0 |
T135 |
1312 |
0 |
0 |
0 |
T136 |
1555 |
0 |
0 |
0 |
T137 |
7641 |
1 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T154 |
0 |
8 |
0 |
0 |
T155 |
0 |
471 |
0 |
0 |
T157 |
0 |
447 |
0 |
0 |
T160 |
0 |
8 |
0 |
0 |
T173 |
2325 |
7 |
0 |
0 |
T174 |
7101 |
0 |
0 |
0 |