Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	12	0	12	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	8676431	1			T4	1		T1	2		T9	1
all_values[1]	8676431	1			T4	1		T1	2		T9	1
all_values[2]	8676431	1			T4	1		T1	2		T9	1
all_values[3]	8676431	1			T4	1		T1	2		T9	1
all_values[4]	8676431	1			T4	1		T1	2		T9	1
all_values[5]	8676431	1			T4	1		T1	2		T9	1
all_values[6]	8676431	1			T4	1		T1	2		T9	1
all_values[7]	8676431	1			T4	1		T1	2		T9	1
all_values[8]	8676431	1			T4	1		T1	2		T9	1
all_values[9]	8676431	1			T4	1		T1	2		T9	1
all_values[10]	8676431	1			T4	1		T1	2		T9	1
all_values[11]	8676431	1			T4	1		T1	2		T9	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100223981

1

T4

12

T1

8

T9

12

auto[1]

3893191

1

T1

16

T3

10

T8

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104040488

1

T4

12

T1

24

T9

12

auto[1]

76684

1

T79

24

T80

41

T86

51

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	8232669	1			T4	1		T1	2		T9	1
all_values[0]	auto[0]	auto[1]	87	1			T79	1		T80	1		T86	2
all_values[0]	auto[1]	auto[0]	443561	1			T8	2		T12	2		T79	4
all_values[0]	auto[1]	auto[1]	114	1			T80	4		T86	3		T87	2
all_values[1]	auto[0]	auto[0]	8391074	1			T4	1		T9	1		T12	2
all_values[1]	auto[0]	auto[1]	95	1			T79	3		T86	1		T229	1
all_values[1]	auto[1]	auto[0]	285164	1			T1	2		T3	2		T8	2
all_values[1]	auto[1]	auto[1]	98	1			T80	1		T86	4		T87	1
all_values[2]	auto[0]	auto[0]	8462367	1			T4	1		T9	1		T3	2
all_values[2]	auto[0]	auto[1]	85	1			T79	1		T80	1		T87	4
all_values[2]	auto[1]	auto[0]	213879	1			T1	2		T12	2		T79	1
all_values[2]	auto[1]	auto[1]	100	1			T79	2		T86	2		T87	1
all_values[3]	auto[0]	auto[0]	8272496	1			T4	1		T9	1		T3	2
all_values[3]	auto[0]	auto[1]	104	1			T79	1		T80	2		T86	3
all_values[3]	auto[1]	auto[0]	403715	1			T1	2		T8	2		T12	2
all_values[3]	auto[1]	auto[1]	116	1			T79	3		T80	2		T86	2
all_values[4]	auto[0]	auto[0]	8340734	1			T4	1		T9	1		T8	2
all_values[4]	auto[0]	auto[1]	98	1			T80	1		T86	1		T87	1
all_values[4]	auto[1]	auto[0]	335495	1			T1	2		T3	2		T79	5
all_values[4]	auto[1]	auto[1]	104	1			T80	1		T86	3		T87	1
all_values[5]	auto[0]	auto[0]	8346010	1			T4	1		T9	1		T3	2
all_values[5]	auto[0]	auto[1]	114	1			T79	2		T80	1		T86	1
all_values[5]	auto[1]	auto[0]	330228	1			T1	2		T8	2		T12	2
all_values[5]	auto[1]	auto[1]	79	1			T79	1		T80	2		T86	2
all_values[6]	auto[0]	auto[0]	8255700	1			T4	1		T9	1		T3	2
all_values[6]	auto[0]	auto[1]	42520	1			T79	2		T80	5		T86	3
all_values[6]	auto[1]	auto[0]	376285	1			T1	2		T12	2		T79	1
all_values[6]	auto[1]	auto[1]	1926	1			T79	1		T80	2		T86	3
all_values[7]	auto[0]	auto[0]	8384071	1			T4	1		T9	1		T79	5
all_values[7]	auto[0]	auto[1]	20881	1			T80	2		T86	3		T87	3
all_values[7]	auto[1]	auto[0]	270717	1			T1	2		T3	2		T8	2
all_values[7]	auto[1]	auto[1]	762	1			T80	3		T86	2		T87	4
all_values[8]	auto[0]	auto[0]	8406607	1			T4	1		T9	1		T3	2
all_values[8]	auto[0]	auto[1]	8269	1			T80	2		T86	4		T228	1
all_values[8]	auto[1]	auto[0]	261258	1			T1	2		T8	2		T80	3
all_values[8]	auto[1]	auto[1]	297	1			T80	2		T86	2		T87	2
all_values[9]	auto[0]	auto[0]	8405416	1			T4	1		T1	2		T9	1
all_values[9]	auto[0]	auto[1]	94	1			T79	3		T86	2		T87	1
all_values[9]	auto[1]	auto[0]	270810	1			T8	2		T12	2		T80	5
all_values[9]	auto[1]	auto[1]	111	1			T79	1		T80	1		T87	3
all_values[10]	auto[0]	auto[0]	8234676	1			T4	1		T1	2		T9	1
all_values[10]	auto[0]	auto[1]	123	1			T79	2		T80	3		T86	5
all_values[10]	auto[1]	auto[0]	441551	1			T3	2		T8	2		T79	1
all_values[10]	auto[1]	auto[1]	81	1			T80	1		T86	1		T87	1
all_values[11]	auto[0]	auto[0]	8419342	1			T4	1		T1	2		T9	1
all_values[11]	auto[0]	auto[1]	349	1			T80	2		T86	1		T87	2
all_values[11]	auto[1]	auto[0]	256663	1			T3	2		T8	2		T12	2
all_values[11]	auto[1]	auto[1]	77	1			T79	1		T80	2		T86	1