---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.InterceptLevel_M	0	0	386538025	0	0	0
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	1477438707	0	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	1477438707	0	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	1477438707	0	0	0
tb.dut.u_rx_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_rxf_overflow.DstPulseCheck_A	0	0	649964973	0	0	0
tb.dut.u_rxf_overflow.SrcPulseCheck_M	0	0	192490671	0	0	0
tb.dut.u_sram_clk_scan.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_sram_rst_scanmux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	1929928785	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	1929928785	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	1929928785	0	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	1929928785	0	0	1607
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tx_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_txf_underflow.DstPulseCheck_A	0	0	649964973	0	0	0
tb.dut.u_txf_underflow.SrcPulseCheck_M	0	0	192492102	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.LockArbDecision_A	0	0	386536807	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.NoReadyValidNoGrant_A	0	0	386536807	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqStaysHighUntilGranted0_M	0	0	386536807	0	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	386536807	0	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.DataKnown_A	0	0	386536807	0	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	386536807	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertKnownO_A	0	0	1929928785	1929792554	0	0
tb.dut.CioSdoEnOKnown	0	0	1929928785	1929792554	0	0
tb.dut.CioSdoEnOffWhenInactive	0	0	1929928785	1929792554	0	0
tb.dut.CsPulseWidth_A	0	0	1929928785	1832360329	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	1929928785	110	0	0
tb.dut.IntrReadbufFlipOKnown	0	0	1929928785	1929792554	0	0
tb.dut.IntrReadbufWatermarkOKnown	0	0	1929928785	1929792554	0	0
tb.dut.IntrRxerrOKnown	0	0	1929928785	1929792554	0	0
tb.dut.IntrRxfOKnown	0	0	1929928785	1929792554	0	0
tb.dut.IntrRxlvlOKnown	0	0	1929928785	1929792554	0	0
tb.dut.IntrRxoverflowOKnown	0	0	1929928785	1929792554	0	0
tb.dut.IntrTpmHeaderNotEmptyOKnown	0	0	1929928785	1929792554	0	0
tb.dut.IntrTxlvlOKnown	0	0	1929928785	1929792554	0	0
tb.dut.IntrTxunderflowOKnown	0	0	1929928785	1929792554	0	0
tb.dut.IntrUploadCmdfifoNotEmptyOKnown	0	0	1929928785	1929792554	0	0
tb.dut.IntrUploadPayloadNotEmptyOKnown	0	0	1929928785	1929792554	0	0
tb.dut.IntrUploadPayloadOverflowOKnown	0	0	1929928785	1929792554	0	0
tb.dut.PayloadStartIdxWidthMatch_A	0	0	1607	1607	0	0
tb.dut.SpiModeKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.TpmEnableWhenTpmCsbIdle_M	0	0	1929928785	339	0	0
tb.dut.TpmRdfifoNotFull_A	0	0	1929928785	283317	0	0
tb.dut.TpmWrPtrMatch_A	0	0	1607	1607	0	0
tb.dut.g_sram_connect[0].ReqAlwaysAccepted_A	0	0	1929928785	11636332	0	0
tb.dut.g_sram_connect[1].ReqAlwaysAccepted_A	0	0	1929928785	2494	0	0
tb.dut.g_sram_connect[2].ReqAlwaysAccepted_A	0	0	1929928785	1856	0	0
tb.dut.scanmodeKnown	0	0	1929928785	1929928785	0	0
tb.dut.spi_device_csr_assert.TlulOOBAddrErr_A	0	0	1932431992	9017	0	0
tb.dut.spi_device_csr_assert.addr_swap_data_rd_A	0	0	1932431992	2688	0	0
tb.dut.spi_device_csr_assert.addr_swap_mask_rd_A	0	0	1932431992	2514	0	0
tb.dut.spi_device_csr_assert.cmd_filter_0_rd_A	0	0	1932431992	8911	0	0
tb.dut.spi_device_csr_assert.cmd_filter_1_rd_A	0	0	1932431992	8976	0	0
tb.dut.spi_device_csr_assert.cmd_filter_2_rd_A	0	0	1932431992	7301	0	0
tb.dut.spi_device_csr_assert.cmd_filter_3_rd_A	0	0	1932431992	7808	0	0
tb.dut.spi_device_csr_assert.cmd_filter_4_rd_A	0	0	1932431992	8635	0	0
tb.dut.spi_device_csr_assert.cmd_filter_5_rd_A	0	0	1932431992	7578	0	0
tb.dut.spi_device_csr_assert.cmd_filter_6_rd_A	0	0	1932431992	7397	0	0
tb.dut.spi_device_csr_assert.cmd_filter_7_rd_A	0	0	1932431992	7346	0	0
tb.dut.spi_device_csr_assert.cmd_info_0_rd_A	0	0	1932431992	4790	0	0
tb.dut.spi_device_csr_assert.cmd_info_10_rd_A	0	0	1932431992	4647	0	0
tb.dut.spi_device_csr_assert.cmd_info_11_rd_A	0	0	1932431992	4762	0	0
tb.dut.spi_device_csr_assert.cmd_info_12_rd_A	0	0	1932431992	4255	0	0
tb.dut.spi_device_csr_assert.cmd_info_13_rd_A	0	0	1932431992	4875	0	0
tb.dut.spi_device_csr_assert.cmd_info_14_rd_A	0	0	1932431992	4756	0	0
tb.dut.spi_device_csr_assert.cmd_info_15_rd_A	0	0	1932431992	4796	0	0
tb.dut.spi_device_csr_assert.cmd_info_16_rd_A	0	0	1932431992	4896	0	0
tb.dut.spi_device_csr_assert.cmd_info_17_rd_A	0	0	1932431992	4978	0	0
tb.dut.spi_device_csr_assert.cmd_info_18_rd_A	0	0	1932431992	4722	0	0
tb.dut.spi_device_csr_assert.cmd_info_19_rd_A	0	0	1932431992	4809	0	0
tb.dut.spi_device_csr_assert.cmd_info_1_rd_A	0	0	1932431992	4672	0	0
tb.dut.spi_device_csr_assert.cmd_info_20_rd_A	0	0	1932431992	4941	0	0
tb.dut.spi_device_csr_assert.cmd_info_21_rd_A	0	0	1932431992	4518	0	0
tb.dut.spi_device_csr_assert.cmd_info_22_rd_A	0	0	1932431992	4480	0	0
tb.dut.spi_device_csr_assert.cmd_info_23_rd_A	0	0	1932431992	4694	0	0
tb.dut.spi_device_csr_assert.cmd_info_2_rd_A	0	0	1932431992	4670	0	0
tb.dut.spi_device_csr_assert.cmd_info_3_rd_A	0	0	1932431992	4576	0	0
tb.dut.spi_device_csr_assert.cmd_info_4_rd_A	0	0	1932431992	5006	0	0
tb.dut.spi_device_csr_assert.cmd_info_5_rd_A	0	0	1932431992	4502	0	0
tb.dut.spi_device_csr_assert.cmd_info_6_rd_A	0	0	1932431992	4401	0	0
tb.dut.spi_device_csr_assert.cmd_info_7_rd_A	0	0	1932431992	4793	0	0
tb.dut.spi_device_csr_assert.cmd_info_8_rd_A	0	0	1932431992	4996	0	0
tb.dut.spi_device_csr_assert.cmd_info_9_rd_A	0	0	1932431992	4697	0	0
tb.dut.spi_device_csr_assert.cmd_info_en4b_rd_A	0	0	1932431992	2910	0	0
tb.dut.spi_device_csr_assert.cmd_info_ex4b_rd_A	0	0	1932431992	2896	0	0
tb.dut.spi_device_csr_assert.cmd_info_wrdi_rd_A	0	0	1932431992	2796	0	0
tb.dut.spi_device_csr_assert.cmd_info_wren_rd_A	0	0	1932431992	2790	0	0
tb.dut.spi_device_csr_assert.control_rd_A	0	0	1932431992	3237	0	0
tb.dut.spi_device_csr_assert.fifo_level_rd_A	0	0	1932431992	2912	0	0
tb.dut.spi_device_csr_assert.intercept_en_rd_A	0	0	1932431992	3402	0	0
tb.dut.spi_device_csr_assert.intr_enable_rd_A	0	0	1932431992	4916	0	0
tb.dut.spi_device_csr_assert.jedec_cc_rd_A	0	0	1932431992	2690	0	0
tb.dut.spi_device_csr_assert.jedec_id_rd_A	0	0	1932431992	3019	0	0
tb.dut.spi_device_csr_assert.mailbox_addr_rd_A	0	0	1932431992	2575	0	0
tb.dut.spi_device_csr_assert.payload_swap_data_rd_A	0	0	1932431992	2665	0	0
tb.dut.spi_device_csr_assert.payload_swap_mask_rd_A	0	0	1932431992	2705	0	0
tb.dut.spi_device_csr_assert.read_threshold_rd_A	0	0	1932431992	2703	0	0
tb.dut.spi_device_csr_assert.rxf_addr_rd_A	0	0	1932431992	2741	0	0
tb.dut.spi_device_csr_assert.tpm_access_0_rd_A	0	0	1932431992	3216	0	0
tb.dut.spi_device_csr_assert.tpm_access_1_rd_A	0	0	1932431992	2811	0	0
tb.dut.spi_device_csr_assert.tpm_cfg_rd_A	0	0	1932431992	3314	0	0
tb.dut.spi_device_csr_assert.tpm_did_vid_rd_A	0	0	1932431992	2821	0	0
tb.dut.spi_device_csr_assert.tpm_int_enable_rd_A	0	0	1932431992	2740	0	0
tb.dut.spi_device_csr_assert.tpm_int_status_rd_A	0	0	1932431992	2588	0	0
tb.dut.spi_device_csr_assert.tpm_int_vector_rd_A	0	0	1932431992	2612	0	0
tb.dut.spi_device_csr_assert.tpm_intf_capability_rd_A	0	0	1932431992	2686	0	0
tb.dut.spi_device_csr_assert.tpm_rid_rd_A	0	0	1932431992	2553	0	0
tb.dut.spi_device_csr_assert.tpm_sts_rd_A	0	0	1932431992	2634	0	0
tb.dut.spi_device_csr_assert.txf_addr_rd_A	0	0	1932431992	2803	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	1932431992	231056819	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	1932431992	1932254472	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	1932431992	270600706	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	1932431992	1932254472	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
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tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1782	1782	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	1932433100	17201274	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	1932431992	8746	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	1932433100	222180858	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	1932433100	243328992	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	1932431992	8608	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	1932433100	231056832	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	1932433100	270600714	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	1932433100	231056832	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	1932433100	270600714	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	1932433100	270600714	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	1932433100	270600714	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	1932431992	6519	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	1932431992	7121	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1782	1782	0	0
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown0	0	0	542912	541305	0	0
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown0	0	0	386537475	386535868	0	0
tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic.selKnown1	0	0	386536219	386534807	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown0	0	0	386536807	386535371	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown0	0	0	386538023	386536416	0	0
tb.dut.u_cmdparse.CmdOnlySelDpKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_cmdparse.OnlyOneDatapath_A	0	0	386536807	77406	0	0
tb.dut.u_cmdparse.SelDpKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_cmdparse.StKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	541305	540042	0	0
tb.dut.u_flash_readbuf_flip_pulse_sync.DstPulseCheck_A	0	0	1929928785	576	0	0
tb.dut.u_flash_readbuf_flip_pulse_sync.SrcPulseCheck_M	0	0	386536807	576	0	0
tb.dut.u_flash_readbuf_watermark_pulse_sync.DstPulseCheck_A	0	0	1929928785	335	0	0
tb.dut.u_flash_readbuf_watermark_pulse_sync.SrcPulseCheck_M	0	0	386536807	335	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	1477438707	1438501198	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	1607	1607	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	1477438707	8846707	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	1477438707	8846707	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	1477438707	1438501198	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	1477438707	1438501198	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	1477438707	8846707	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	1477438707	8846707	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	1477438707	8846707	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	1477438707	8846707	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	1477438707	583	0	707
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	1477438707	1438501198	0	0
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	1477438707	8846707	0	0
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo.DataKnown_A	0	0	1477438707	4276807	0	0
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo.DepthKnown_A	0	0	1477438707	1438501198	0	0
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo.RvalidKnown_A	0	0	1477438707	1438501198	0	0
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo.WreadyKnown_A	0	0	1477438707	1438501198	0	0
tb.dut.u_fwmode.u_fwmode_arb.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1477438707	4276807	0	0
tb.dut.u_fwmode.u_rx_fifo.GrayRptr_A	0	0	1477438707	1477432035	0	0
tb.dut.u_fwmode.u_rx_fifo.GrayWptr_A	0	0	386536807	386535263	0	0
tb.dut.u_fwmode.u_rx_fifo.ParamCheckDepth_A	0	0	1607	1607	0	0
tb.dut.u_fwmode.u_tx_fifo.GrayRptr_A	0	0	386538023	386534941	0	0
tb.dut.u_fwmode.u_tx_fifo.GrayWptr_A	0	0	1477438707	1477431838	0	0
tb.dut.u_fwmode.u_tx_fifo.ParamCheckDepth_A	0	0	1607	1607	0	0
tb.dut.u_intr_cmdfifo_not_empty.IntrTKind_A	0	0	1607	1607	0	0
tb.dut.u_intr_payload_not_empty.IntrTKind_A	0	0	1607	1607	0	0
tb.dut.u_intr_payload_overflow.IntrTKind_A	0	0	1607	1607	0	0
tb.dut.u_intr_readbuf_flip.IntrTKind_A	0	0	1607	1607	0	0
tb.dut.u_intr_readbuf_watermark.IntrTKind_A	0	0	1607	1607	0	0
tb.dut.u_intr_rxerr.IntrTKind_A	0	0	1607	1607	0	0
tb.dut.u_intr_rxf.IntrTKind_A	0	0	1607	1607	0	0
tb.dut.u_intr_rxlvl.IntrTKind_A	0	0	1607	1607	0	0
tb.dut.u_intr_rxoverflow.IntrTKind_A	0	0	1607	1607	0	0
tb.dut.u_intr_tpm_cmdaddr_notempty.IntrTKind_A	0	0	1607	1607	0	0
tb.dut.u_intr_txlvl.IntrTKind_A	0	0	1607	1607	0	0
tb.dut.u_intr_txunderflow.IntrTKind_A	0	0	1607	1607	0	0
tb.dut.u_jedec.JedecStKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_memory_2p.CannotHaveEccAndParity_A	0	0	1607	1607	0	0
tb.dut.u_memory_2p.gen_byte_parity.ParityNeedsByteWriteMask_A	0	0	1607	1607	0	0
tb.dut.u_memory_2p.gen_byte_parity.WidthNeedsToBeByteAligned_A	0	0	1607	1607	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortA_A	0	0	1929928785	7019590	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheckPortB_A	0	0	1477438707	5282607	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortA_A	0	0	1929928785	7019590	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[1].MaskCheckPortB_A	0	0	1477438707	5282607	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortA_A	0	0	1929928785	7019590	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[2].MaskCheckPortB_A	0	0	1477438707	5282607	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortA_A	0	0	1929928785	7019590	0	0
tb.dut.u_memory_2p.u_mem.gen_generic.u_impl_generic.gen_wmask[3].MaskCheckPortB_A	0	0	1477438707	5282607	0	0
tb.dut.u_p2s.IoModeChangeValid_A	0	0	386538023	9969	0	0
tb.dut.u_p2s.IoModeDefault_A	0	0	386538023	63920	0	0
tb.dut.u_passthrough.AddrSetInStIdle_A	0	0	9705	9705	0	0
tb.dut.u_passthrough.PassThroughStKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_passthrough.PayloadSwapConstraint_M	0	0	386536807	2225624	0	0
tb.dut.u_readcmd.AddrIncNotAssertInAddressState_A	0	0	386536807	6274713	0	0
tb.dut.u_readcmd.MailboxSizeMatch_M	0	0	386536807	335033634	0	0
tb.dut.u_readcmd.ValidCmdConfig_A	0	0	386536807	273133	0	0
tb.dut.u_readcmd.u_readbuffer.StartWithAddressUpdate_A	0	0	386536807	10315	0	0
tb.dut.u_readcmd.u_readsram.AddrLatchedPulse_M	0	0	386536807	525341	0	0
tb.dut.u_readcmd.u_readsram.FifoNotEmpty_A	0	0	386536807	6274713	0	0
tb.dut.u_readcmd.u_readsram.NotOverflow_A	0	0	386536807	1581498	0	0
tb.dut.u_readcmd.u_readsram.ReqStrbRelation_M	0	0	386536807	10315	0	0
tb.dut.u_readcmd.u_readsram.SramDataReturnRequirement_M	0	0	386536807	1580868	0	0
tb.dut.u_readcmd.u_readsram.SramReadOnly_A	0	0	386536807	1581498	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.DataKnown_A	0	0	386536807	31915957	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.DepthKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.RvalidKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.WreadyKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_readcmd.u_readsram.u_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	386536807	31915957	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DataKnown_A	0	0	386536807	30365404	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.DepthKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.RvalidKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.WreadyKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_readcmd.u_readsram.u_sram_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	386536807	30365404	0	0
tb.dut.u_reg.en2addrHit	0	0	1932431992	161587174	0	0
tb.dut.u_reg.reAfterRv	0	0	1932431992	161587172	0	0
tb.dut.u_reg.rePulse	0	0	1932431992	155955552	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1782	1782	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1782	1782	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1782	1782	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1782	1782	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1782	1782	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1782	1782	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1782	1782	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1782	1782	0	0
tb.dut.u_reg.u_socket.NotOverflowed_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	1932431992	231056819	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1782	1782	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	1932431992	270600706	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1782	1782	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	1932431992	13683788	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1782	1782	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	1932431992	23182205	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1782	1782	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	1932431992	212658785	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1782	1782	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	1932431992	247418501	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	1932431992	1932254472	0	0
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1782	1782	0	0
tb.dut.u_reg.u_socket.maxN	0	0	1782	1782	0	0
tb.dut.u_reg.wePulse	0	0	1932431992	5631620	0	0
tb.dut.u_rx_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	1846	239	0	0
tb.dut.u_s2p.IoModeDefault_A	0	0	386536807	63931	0	0
tb.dut.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	1607	1607	0	0
tb.dut.u_scanmode_sync.OutputsKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	1929928785	1929792554	0	0
tb.dut.u_spi_tpm.CmdAddrAvailable_A	0	0	386536807	72892	0	0
tb.dut.u_spi_tpm.CmdAddrBitCntInAddrSt_A	0	0	386536807	784792	0	0
tb.dut.u_spi_tpm.CmdAddrInfo_A	0	0	386536807	78629	0	0
tb.dut.u_spi_tpm.CmdPowerof2_A	0	0	1607	1607	0	0
tb.dut.u_spi_tpm.DataFifoLessThan64_A	0	0	1607	1607	0	0
tb.dut.u_spi_tpm.DataSelKnown_A	0	0	386538023	37058304	0	0
tb.dut.u_spi_tpm.HwRegCondition2_a	0	0	386536807	15813	0	0
tb.dut.u_spi_tpm.HwRegCondition_A	0	0	386536807	98099	0	0
tb.dut.u_spi_tpm.HwRegIdxKnown_A	0	0	386538023	37058304	0	0
tb.dut.u_spi_tpm.LocalityLatchCondition_A	0	0	386536807	98099	0	0
tb.dut.u_spi_tpm.RdFifoDepthPoT_A	0	0	1607	1607	0	0
tb.dut.u_spi_tpm.RdFifoNumBytesPoT_A	0	0	1607	1607	0	0
tb.dut.u_spi_tpm.RdPowerof2_A	0	0	1607	1607	0	0
tb.dut.u_spi_tpm.SckFifoAddrLatchCondition_A	0	0	386536807	98099	0	0
tb.dut.u_spi_tpm.TpmRegCondition_A	0	0	386536807	98099	0	0
tb.dut.u_spi_tpm.TpmRegSizeMatch_A	0	0	1607	1607	0	0
tb.dut.u_spi_tpm.WrDepthSpec_A	0	0	1607	1607	0	0
tb.dut.u_spi_tpm.WrFifoAvailable_A	0	0	386536807	631029	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayRptr_A	0	0	1929928785	1929790756	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.GrayWptr_A	0	0	386536807	386535311	0	0
tb.dut.u_spi_tpm.u_cmdaddr_buffer.ParamCheckDepth_A	0	0	1607	1607	0	0
tb.dut.u_spi_tpm.u_hw_reg_slice.ValidWidth_A	0	0	1607	1607	0	0
tb.dut.u_spi_tpm.u_rdfifo.GrayRptr_A	0	0	386538023	36960205	0	0
tb.dut.u_spi_tpm.u_rdfifo.GrayWptr_A	0	0	1929928785	97184615	0	0
tb.dut.u_spi_tpm.u_rdfifo.ParamCheckDepth_A	0	0	1607	1607	0	0
tb.dut.u_spi_tpm.u_wrfifo.GrayRptr_A	0	0	1929928785	1929790756	0	0
tb.dut.u_spi_tpm.u_wrfifo.GrayWptr_A	0	0	386536807	386535311	0	0
tb.dut.u_spi_tpm.u_wrfifo.ParamCheckDepth_A	0	0	1607	1607	0	0
tb.dut.u_spid_status.BusyBitZero_A	0	0	1607	1607	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.GrayRptr_A	0	0	386536807	386535311	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.GrayWptr_A	0	0	1929928785	1929790756	0	0
tb.dut.u_spid_status.u_sw_status_update_sync.ParamCheckDepth_A	0	0	1607	1607	0	0
tb.dut.u_sram_clk_scan.gen_generic.u_impl_generic.selKnown0	0	0	1477438707	1477437245	0	0
tb.dut.u_sram_clk_sel.gen_generic.u_impl_generic.selKnown0	0	0	386536807	386535371	0	0
tb.dut.u_sram_clk_sel.gen_generic.u_impl_generic.selKnown1	0	0	1929928785	1929927178	0	0
tb.dut.u_sram_rst_scanmux.gen_generic.u_impl_generic.selKnown0	0	0	78606	77293	0	0
tb.dut.u_sram_rst_sel.gen_generic.u_impl_generic.selKnown0	0	0	541305	540042	0	0
tb.dut.u_sram_rst_sel.gen_generic.u_impl_generic.selKnown1	0	0	1798	191	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	1929928785	1929792554	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	1607	1607	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	1929928785	11640682	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	1929928785	11640682	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	1929928785	11640682	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	1929928785	11640682	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	1929928785	11640682	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	1929928785	11640682	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	1929928785	11640682	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.DataKnown_A	0	0	1929928785	4621092	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.DepthKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.RvalidKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.WreadyKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_sys_sram_arbiter.u_req_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1929928785	4621092	0	0
tb.dut.u_tlul2sram.AddrOutKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.DataIntgOptions_A	0	0	1607	1607	0	0
tb.dut.u_tlul2sram.ReqOutKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.SramDwHasByteGranularity_A	0	0	1607	1607	0	0
tb.dut.u_tlul2sram.SramDwIsMultipleOfTlulWidth_A	0	0	1607	1607	0	0
tb.dut.u_tlul2sram.TlOutKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.TlOutPayloadKnown_A	0	0	1929928785	23095223	0	0
tb.dut.u_tlul2sram.TlOutPayloadKnown_AKnownEnable	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.WdataOutKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.WeOutKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.WmaskOutKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.adapterNoReadOrWrite	0	0	1607	1607	0	0
tb.dut.u_tlul2sram.rvalidHighReqFifoEmpty	0	0	1929928785	4616742	0	0
tb.dut.u_tlul2sram.rvalidHighWhenRspFifoFull	0	0	1929928785	4616742	0	0
tb.dut.u_tlul2sram.u_err.dataWidthOnly32_A	0	0	1607	1607	0	0
tb.dut.u_tlul2sram.u_reqfifo.DataKnown_A	0	0	1929928785	23095223	0	0
tb.dut.u_tlul2sram.u_reqfifo.DepthKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.u_reqfifo.RvalidKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.u_reqfifo.WreadyKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1929928785	23095223	0	0
tb.dut.u_tlul2sram.u_rsp_gen.DataWidthCheck_A	0	0	1607	1607	0	0
tb.dut.u_tlul2sram.u_rsp_gen.PayLoadWidthCheck	0	0	1607	1607	0	0
tb.dut.u_tlul2sram.u_rspfifo.DataKnown_A	0	0	1929928785	9593372	0	0
tb.dut.u_tlul2sram.u_rspfifo.DepthKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.u_rspfifo.RvalidKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.u_rspfifo.WreadyKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1929928785	9593372	0	0
tb.dut.u_tlul2sram.u_sramreqfifo.DataKnown_A	0	0	1929928785	4616742	0	0
tb.dut.u_tlul2sram.u_sramreqfifo.DepthKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.u_sramreqfifo.RvalidKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.u_sramreqfifo.WreadyKnown_A	0	0	1929928785	1929792554	0	0
tb.dut.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	1929928785	4616742	0	0
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	123431	122976	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	122146	121691	0	0
tb.dut.u_tx_rst_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	1848	241	0	0
tb.dut.u_upload.AddrFifoNeverFull_M	0	0	386536807	1856	0	0
tb.dut.u_upload.CmdFifoNeverFull_M	0	0	386536807	2494	0	0
tb.dut.u_upload.CmdFifoPush_A	0	0	386536807	2494	0	0
tb.dut.u_upload.FifosOnlyOneValid_A	0	0	386536807	335033634	0	0
tb.dut.u_upload.PayloadNeverFull_M	0	0	386536807	708357	0	0
tb.dut.u_upload.u_addrfifo.MinDepth_A	0	0	1607	1607	0	0
tb.dut.u_upload.u_addrfifo.NoRAckInEmpty_A	0	0	1929928785	1856	0	0
tb.dut.u_upload.u_addrfifo.NoWAckInFull_A	0	0	386536807	1856	0	0
tb.dut.u_upload.u_addrfifo.ParamCheckDepth_A	0	0	1607	1607	0	0
tb.dut.u_upload.u_addrfifo.RSramRvalidOneCycle_M	0	0	1929928785	1856	0	0
tb.dut.u_upload.u_addrfifo.RptrGrayOneBitAtATime_A	0	0	1929928785	1856	0	0
tb.dut.u_upload.u_addrfifo.RptrIncDataValid_A	0	0	1929928785	1856	0	0
tb.dut.u_upload.u_addrfifo.RptrIncrease_A	0	0	1929928785	1856	0	0
tb.dut.u_upload.u_addrfifo.SramRvalid_A	0	0	1929928785	1856	0	0
tb.dut.u_upload.u_addrfifo.WSramRvalid_A	0	0	386536807	386536801	0	0
tb.dut.u_upload.u_addrfifo.WidthMatch_A	0	0	1607	1607	0	0
tb.dut.u_upload.u_addrfifo.WptrGrayOneBitAtATime_A	0	0	386536807	1856	0	0
tb.dut.u_upload.u_addrfifo.WptrIncrease_A	0	0	386536807	1856	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckHotOne_A	0	0	386536807	335033634	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.CheckNGreaterZero_A	0	0	1607	1607	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesReady_A	0	0	386536807	712707	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GntImpliesValid_A	0	0	386536807	712707	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.GrantKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IdxKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.IndexIsCorrect_A	0	0	386536807	712707	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReadyAndValidImplyGrant_A	0	0	386536807	712707	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqAndReadyImplyGrant_A	0	0	386536807	712707	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ReqImpliesValid_A	0	0	386536807	712707	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.ValidKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb.gen_data_port_assertion.DataFlow_A	0	0	386536807	712707	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.DepthKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.RvalidKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_upload.u_arbiter.u_req_fifo.WreadyKnown_A	0	0	386536807	335033634	0	0
tb.dut.u_upload.u_cmdfifo.MinDepth_A	0	0	1607	1607	0	0
tb.dut.u_upload.u_cmdfifo.NoRAckInEmpty_A	0	0	1929928785	2494	0	0
tb.dut.u_upload.u_cmdfifo.NoWAckInFull_A	0	0	386536807	2494	0	0
tb.dut.u_upload.u_cmdfifo.ParamCheckDepth_A	0	0	1607	1607	0	0
tb.dut.u_upload.u_cmdfifo.RSramRvalidOneCycle_M	0	0	1929928785	2494	0	0
tb.dut.u_upload.u_cmdfifo.RptrGrayOneBitAtATime_A	0	0	1929928785	2494	0	0
tb.dut.u_upload.u_cmdfifo.RptrIncDataValid_A	0	0	1929928785	2494	0	0
tb.dut.u_upload.u_cmdfifo.RptrIncrease_A	0	0	1929928785	2494	0	0
tb.dut.u_upload.u_cmdfifo.SramRvalid_A	0	0	1929928785	2494	0	0
tb.dut.u_upload.u_cmdfifo.WSramRvalid_A	0	0	386536807	386536801	0	0
tb.dut.u_upload.u_cmdfifo.WidthMatch_A	0	0	1607	1607	0	0
tb.dut.u_upload.u_cmdfifo.WptrGrayOneBitAtATime_A	0	0	386536807	2494	0	0
tb.dut.u_upload.u_cmdfifo.WptrIncrease_A	0	0	386536807	2494	0	0
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.NumEntryPerWordPowerOf2_A	0	0	1607	1607	0	0
tb.dut.u_upload.u_payload_buffer.g_multiple_entry_per_word.WidthDivideSramDw_A	0	0	1607	1607	0	0
tb.dut.u_upload.u_payloadptr_clr_psync.DstPulseCheck_A	0	0	1929928785	2494	0	0
tb.dut.u_upload.u_payloadptr_clr_psync.SrcPulseCheck_M	0	0	386536807	2494	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_fwmode.u_fwmode_arb.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	1477438707	583	0	707
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb.RoundRobin_A	0	0	1929928785	0	0	1607

Assertions Without Attempts:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_rx_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_sram_clk_scan.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_sram_rst_scanmux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0
tb.dut.u_tx_rst_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	0	0	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	1932433100	3147203	3147203	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	1932433100	3824	3824	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	1932433100	3807	3807	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	1932433100	2671	2671	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	1932433100	298	298	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	1932433100	2025	2025	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	1932433100	656	656	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	1932433100	11004	11004	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	1932433100	43465511	43465511	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	1932433100	62747151	62747151	1762

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	1932433100	3147203	3147203	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	1932433100	3824	3824	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	1932433100	3807	3807	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	1932433100	2671	2671	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	1932433100	298	298	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	1932433100	2025	2025	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	1932433100	656	656	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	1932433100	11004	11004	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	1932433100	43465511	43465511	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	1932433100	62747151	62747151	1762