Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.10	99.01	96.33	98.63	92.06	98.05	95.86	99.76

Total tests in report: 1782

---

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
60.55	60.55	92.21	92.21	79.12	79.12	63.80	63.80	19.67	19.67	88.43	88.43	73.26	73.26	7.34	7.34	/workspace/coverage/default/25.spi_device_mailbox.3750962473
73.85	13.31	95.12	2.91	83.60	4.48	66.93	3.13	67.21	47.54	92.50	4.06	80.65	7.39	30.97	23.63	/workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.798798902
82.88	9.02	97.16	2.04	90.47	6.87	89.24	22.31	85.25	18.03	95.55	3.05	83.90	3.25	38.59	7.62	/workspace/coverage/default/19.spi_device_extreme_fifo_size.2908971247
88.10	5.22	97.53	0.37	91.70	1.23	89.53	0.29	93.44	8.20	96.12	0.58	84.49	0.59	63.89	25.30	/workspace/coverage/default/30.spi_device_stress_all.687705078
90.07	1.97	98.33	0.81	93.26	1.56	90.61	1.08	93.44	0.00	97.44	1.32	93.35	8.86	64.03	0.14	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2132123707
91.31	1.24	98.57	0.23	93.78	0.52	92.76	2.15	93.44	0.00	97.44	0.00	93.35	0.00	69.80	5.76	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.97685210
92.40	1.09	98.62	0.06	93.86	0.08	92.76	0.00	93.44	0.00	97.56	0.12	93.35	0.00	77.18	7.38	/workspace/coverage/default/15.spi_device_flash_all.1229195056
92.99	0.59	98.65	0.03	94.85	0.99	93.54	0.78	93.44	0.00	97.58	0.02	94.09	0.74	78.75	1.57	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1969930335
93.55	0.56	98.66	0.01	94.85	0.00	97.46	3.91	93.44	0.00	97.58	0.00	94.09	0.00	78.75	0.00	/workspace/coverage/default/10.spi_device_ram_cfg.1626642302
94.10	0.55	98.66	0.00	94.85	0.00	97.46	0.00	93.44	0.00	97.58	0.00	94.09	0.00	82.61	3.86	/workspace/coverage/default/21.spi_device_flash_all.2305819606
94.47	0.37	98.66	0.00	94.86	0.01	97.46	0.00	93.44	0.00	97.58	0.00	94.09	0.00	85.18	2.57	/workspace/coverage/default/11.spi_device_stress_all.3945140488
94.75	0.28	98.66	0.00	94.86	0.00	97.46	0.00	93.44	0.00	97.58	0.00	94.09	0.00	87.14	1.95	/workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3402262173
95.02	0.28	98.72	0.06	95.03	0.16	97.46	0.00	95.08	1.64	97.65	0.07	94.09	0.00	87.14	0.00	/workspace/coverage/default/43.spi_device_rx_timeout.1547553959
95.26	0.24	98.73	0.02	95.08	0.05	98.24	0.78	95.08	0.00	97.68	0.03	94.09	0.00	87.95	0.81	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.476785099
95.49	0.23	98.73	0.00	95.09	0.01	98.24	0.00	95.08	0.00	97.68	0.00	94.09	0.00	89.52	1.57	/workspace/coverage/default/24.spi_device_stress_all.531259961
95.71	0.22	98.85	0.11	95.43	0.34	98.24	0.00	95.08	0.00	97.83	0.15	94.68	0.59	89.85	0.33	/workspace/coverage/default/44.spi_device_flash_mode.1874849766
95.90	0.19	98.85	0.00	95.44	0.01	98.24	0.00	95.08	0.00	97.83	0.00	94.68	0.00	91.14	1.29	/workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3985374575
96.07	0.17	99.02	0.17	95.44	0.00	98.24	0.00	95.08	0.00	97.83	0.00	94.68	0.00	92.19	1.05	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.143383959
96.22	0.15	99.02	0.00	95.44	0.00	98.24	0.00	95.08	0.00	97.83	0.00	94.68	0.00	93.23	1.05	/workspace/coverage/default/32.spi_device_stress_all.3403511592
96.35	0.13	99.02	0.00	95.44	0.00	98.24	0.00	95.08	0.00	97.83	0.00	95.57	0.89	93.23	0.00	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1074225889
96.46	0.12	99.04	0.03	95.99	0.55	98.24	0.00	95.08	0.00	97.88	0.05	95.57	0.00	93.43	0.19	/workspace/coverage/default/19.spi_device_intr.3288735231
96.58	0.12	99.04	0.00	95.99	0.00	98.24	0.00	95.08	0.00	97.88	0.00	95.57	0.00	94.24	0.81	/workspace/coverage/default/31.spi_device_flash_all.2267648794
96.68	0.10	99.04	0.00	95.99	0.00	98.24	0.00	95.08	0.00	97.88	0.00	95.57	0.00	94.95	0.71	/workspace/coverage/default/28.spi_device_stress_all.2568980947
96.77	0.09	99.05	0.01	95.99	0.00	98.24	0.00	95.08	0.00	97.90	0.02	95.57	0.00	95.57	0.62	/workspace/coverage/default/49.spi_device_tpm_all.2589762183
96.85	0.08	99.05	0.00	95.99	0.00	98.24	0.00	95.08	0.00	97.90	0.00	95.57	0.00	96.14	0.57	/workspace/coverage/default/37.spi_device_stress_all.977652455
96.92	0.07	99.05	0.00	96.03	0.04	98.24	0.00	95.08	0.00	97.90	0.00	95.57	0.00	96.57	0.43	/workspace/coverage/default/27.spi_device_bit_transfer.17861041
96.99	0.07	99.05	0.00	96.05	0.03	98.43	0.20	95.08	0.00	97.90	0.00	95.72	0.15	96.67	0.10	/workspace/coverage/default/0.spi_device_sec_cm.3738359098
97.04	0.05	99.10	0.05	96.05	0.00	98.43	0.00	95.08	0.00	97.93	0.03	95.86	0.15	96.81	0.14	/workspace/coverage/default/46.spi_device_stress_all.1170533758
97.08	0.04	99.10	0.00	96.05	0.00	98.43	0.00	95.08	0.00	97.93	0.00	95.86	0.00	97.09	0.29	/workspace/coverage/default/0.spi_device_flash_all.381179849
97.11	0.03	99.10	0.00	96.05	0.00	98.43	0.00	95.08	0.00	97.93	0.00	95.86	0.00	97.33	0.24	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.3598079592
97.15	0.03	99.10	0.00	96.05	0.00	98.43	0.00	95.08	0.00	97.93	0.00	95.86	0.00	97.57	0.24	/workspace/coverage/default/13.spi_device_stress_all.2083011650
97.18	0.03	99.10	0.00	96.05	0.00	98.43	0.00	95.08	0.00	97.93	0.00	95.86	0.00	97.81	0.24	/workspace/coverage/default/22.spi_device_flash_and_tpm.1336975203
97.22	0.03	99.16	0.06	96.14	0.09	98.43	0.00	95.08	0.00	98.02	0.08	95.86	0.00	97.81	0.00	/workspace/coverage/default/0.spi_device_mem_parity.2199966434
97.25	0.03	99.16	0.00	96.17	0.03	98.63	0.20	95.08	0.00	98.02	0.00	95.86	0.00	97.81	0.00	/workspace/coverage/default/20.spi_device_alert_test.354762972
97.27	0.03	99.16	0.00	96.17	0.00	98.63	0.00	95.08	0.00	98.02	0.00	95.86	0.00	98.00	0.19	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.973160092
97.30	0.03	99.16	0.00	96.17	0.00	98.63	0.00	95.08	0.00	98.02	0.00	95.86	0.00	98.19	0.19	/workspace/coverage/default/14.spi_device_stress_all.3699245216
97.32	0.02	99.16	0.00	96.17	0.00	98.63	0.00	95.08	0.00	98.02	0.00	95.86	0.00	98.33	0.14	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3801479421
97.34	0.02	99.16	0.00	96.17	0.00	98.63	0.00	95.08	0.00	98.02	0.00	95.86	0.00	98.48	0.14	/workspace/coverage/default/24.spi_device_intr.1972163412
97.36	0.02	99.16	0.00	96.17	0.00	98.63	0.00	95.08	0.00	98.02	0.00	95.86	0.00	98.62	0.14	/workspace/coverage/default/6.spi_device_flash_mode.149842239
97.38	0.01	99.16	0.00	96.27	0.10	98.63	0.00	95.08	0.00	98.02	0.00	95.86	0.00	98.62	0.00	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1297345731
97.39	0.01	99.16	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.02	0.00	95.86	0.00	98.71	0.10	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.2676858865
97.40	0.01	99.16	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.02	0.00	95.86	0.00	98.81	0.10	/workspace/coverage/default/10.spi_device_fifo_underflow_overflow.939145228
97.42	0.01	99.16	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.02	0.00	95.86	0.00	98.90	0.10	/workspace/coverage/default/17.spi_device_flash_all.3224817013
97.43	0.01	99.16	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.02	0.00	95.86	0.00	99.00	0.10	/workspace/coverage/default/26.spi_device_flash_and_tpm.1031693583
97.45	0.01	99.16	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.02	0.00	95.86	0.00	99.09	0.10	/workspace/coverage/default/43.spi_device_intr.4030582641
97.46	0.01	99.16	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.02	0.00	95.86	0.00	99.19	0.10	/workspace/coverage/default/8.spi_device_flash_all.3446631464
97.47	0.01	99.17	0.01	96.27	0.00	98.63	0.00	95.08	0.00	98.04	0.02	95.86	0.00	99.24	0.05	/workspace/coverage/default/22.spi_device_intercept.3643613240
97.48	0.01	99.17	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.04	0.00	95.86	0.00	99.29	0.05	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4130428583
97.48	0.01	99.17	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.04	0.00	95.86	0.00	99.33	0.05	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.268299621
97.49	0.01	99.17	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.04	0.00	95.86	0.00	99.38	0.05	/workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2505212431
97.50	0.01	99.17	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.04	0.00	95.86	0.00	99.43	0.05	/workspace/coverage/default/10.spi_device_extreme_fifo_size.4237383482
97.50	0.01	99.17	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.04	0.00	95.86	0.00	99.48	0.05	/workspace/coverage/default/10.spi_device_stress_all.2372216141
97.51	0.01	99.17	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.04	0.00	95.86	0.00	99.52	0.05	/workspace/coverage/default/15.spi_device_flash_mode.4060893999
97.52	0.01	99.17	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.04	0.00	95.86	0.00	99.57	0.05	/workspace/coverage/default/16.spi_device_stress_all.2988261983
97.52	0.01	99.17	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.04	0.00	95.86	0.00	99.62	0.05	/workspace/coverage/default/18.spi_device_flash_all.2964425523
97.53	0.01	99.17	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.04	0.00	95.86	0.00	99.67	0.05	/workspace/coverage/default/21.spi_device_intr.3489740327
97.54	0.01	99.17	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.04	0.00	95.86	0.00	99.71	0.05	/workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1034078662
97.54	0.01	99.17	0.00	96.27	0.00	98.63	0.00	95.08	0.00	98.04	0.00	95.86	0.00	99.76	0.05	/workspace/coverage/default/7.spi_device_stress_all.3745100805
97.55	0.01	99.18	0.01	96.28	0.01	98.63	0.00	95.08	0.00	98.05	0.02	95.86	0.00	99.76	0.00	/workspace/coverage/default/17.spi_device_abort.634037717
97.55	0.01	99.18	0.00	96.29	0.01	98.63	0.00	95.08	0.00	98.05	0.00	95.86	0.00	99.76	0.00	/workspace/coverage/default/0.spi_device_rx_async_fifo_reset.2710937376
97.55	0.01	99.18	0.00	96.31	0.01	98.63	0.00	95.08	0.00	98.05	0.00	95.86	0.00	99.76	0.00	/workspace/coverage/default/0.spi_device_tx_async_fifo_reset.2877918023
97.56	0.01	99.18	0.00	96.32	0.01	98.63	0.00	95.08	0.00	98.05	0.00	95.86	0.00	99.76	0.00	/workspace/coverage/default/15.spi_device_upload.3832765323
97.56	0.01	99.18	0.00	96.33	0.01	98.63	0.00	95.08	0.00	98.05	0.00	95.86	0.00	99.76	0.00	/workspace/coverage/default/16.spi_device_dummy_item_extra_dly.3844427143

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3916670638
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2735160713
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.597285142
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2206919976
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3987155063
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.635299100
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1057336455
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2456777598
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4035835543
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1303203789
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.67150007
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1072278109
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3833316864
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.3163248951
/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2102688938
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4007755316
/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4217560174
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2506660843
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3783183532
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1334360523
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4246092276
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.1408024305
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2946733178
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1545828100
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3775942759
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3758581355
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2889202040
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.3607146884
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2892927587
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3368986987
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1454010679
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1785088052
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1320922378
/workspace/coverage/cover_reg_top/12.spi_device_intr_test.4091848329
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3785828091
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.921185772
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2624104223
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1642540526
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1247086664
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1516223846
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.701919141
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3068818604
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2405927684
/workspace/coverage/cover_reg_top/14.spi_device_intr_test.662698470
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.338397950
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3687053282
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.142812907
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1043197184
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4079876717
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.4096623825
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.557022532
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4164710340
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.657940121
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.324090515
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1289554681
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.1328026366
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3074653055
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.598071670
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1953966864
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.853638295
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.3165535478
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2468116329
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.828260315
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2772002269
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2368005454
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4285448402
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.2426687670
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.821273054
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4225546696
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.359561980
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/workspace/coverage/default/6.spi_device_abort.3103052737
/workspace/coverage/default/6.spi_device_alert_test.842642686
/workspace/coverage/default/6.spi_device_bit_transfer.826761608
/workspace/coverage/default/6.spi_device_byte_transfer.872606321
/workspace/coverage/default/6.spi_device_cfg_cmd.1719611225
/workspace/coverage/default/6.spi_device_csb_read.2814133485
/workspace/coverage/default/6.spi_device_dummy_item_extra_dly.4222536508
/workspace/coverage/default/6.spi_device_extreme_fifo_size.3292910345
/workspace/coverage/default/6.spi_device_fifo_full.1987516522
/workspace/coverage/default/6.spi_device_fifo_underflow_overflow.3206505949
/workspace/coverage/default/6.spi_device_flash_and_tpm.2953473585
/workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1360799816
/workspace/coverage/default/6.spi_device_intercept.3983961860
/workspace/coverage/default/6.spi_device_intr.3592591390
/workspace/coverage/default/6.spi_device_mailbox.1917400481
/workspace/coverage/default/6.spi_device_mem_parity.2382929140
/workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4026994603
/workspace/coverage/default/6.spi_device_pass_cmd_filtering.4182394610
/workspace/coverage/default/6.spi_device_perf.1869061883
/workspace/coverage/default/6.spi_device_ram_cfg.2527954545
/workspace/coverage/default/6.spi_device_read_buffer_direct.2064658171
/workspace/coverage/default/6.spi_device_rx_async_fifo_reset.4082699237
/workspace/coverage/default/6.spi_device_rx_timeout.3941449290
/workspace/coverage/default/6.spi_device_smoke.1435680125
/workspace/coverage/default/6.spi_device_stress_all.430866926
/workspace/coverage/default/6.spi_device_tpm_all.322150943
/workspace/coverage/default/6.spi_device_tpm_read_hw_reg.271610400
/workspace/coverage/default/6.spi_device_tpm_rw.2956362057
/workspace/coverage/default/6.spi_device_tpm_sts_read.3093576967
/workspace/coverage/default/6.spi_device_tx_async_fifo_reset.261528032
/workspace/coverage/default/6.spi_device_txrx.128177780
/workspace/coverage/default/6.spi_device_upload.3175660301
/workspace/coverage/default/7.spi_device_abort.647890747
/workspace/coverage/default/7.spi_device_alert_test.3709422901
/workspace/coverage/default/7.spi_device_bit_transfer.2087217721
/workspace/coverage/default/7.spi_device_byte_transfer.3359493141
/workspace/coverage/default/7.spi_device_cfg_cmd.2505724825
/workspace/coverage/default/7.spi_device_csb_read.706018819
/workspace/coverage/default/7.spi_device_dummy_item_extra_dly.1902522336
/workspace/coverage/default/7.spi_device_extreme_fifo_size.4242987357
/workspace/coverage/default/7.spi_device_fifo_full.3127781295
/workspace/coverage/default/7.spi_device_fifo_underflow_overflow.3955918027
/workspace/coverage/default/7.spi_device_flash_all.2793843872
/workspace/coverage/default/7.spi_device_flash_and_tpm.700566543
/workspace/coverage/default/7.spi_device_flash_mode.861226835
/workspace/coverage/default/7.spi_device_intercept.1723348470
/workspace/coverage/default/7.spi_device_intr.3067322449
/workspace/coverage/default/7.spi_device_mailbox.1721169543
/workspace/coverage/default/7.spi_device_mem_parity.3433820186
/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.452436747
/workspace/coverage/default/7.spi_device_pass_cmd_filtering.2981971135
/workspace/coverage/default/7.spi_device_perf.1359021451
/workspace/coverage/default/7.spi_device_ram_cfg.2033602589
/workspace/coverage/default/7.spi_device_read_buffer_direct.3493026762
/workspace/coverage/default/7.spi_device_rx_async_fifo_reset.3196263472
/workspace/coverage/default/7.spi_device_rx_timeout.1852833793
/workspace/coverage/default/7.spi_device_smoke.670576146
/workspace/coverage/default/7.spi_device_tpm_all.2192130241
/workspace/coverage/default/7.spi_device_tpm_read_hw_reg.378431781
/workspace/coverage/default/7.spi_device_tpm_rw.124412693
/workspace/coverage/default/7.spi_device_tpm_sts_read.3958046232
/workspace/coverage/default/7.spi_device_tx_async_fifo_reset.2808346749
/workspace/coverage/default/7.spi_device_txrx.1918075096
/workspace/coverage/default/7.spi_device_upload.1864178721
/workspace/coverage/default/8.spi_device_abort.4066539249
/workspace/coverage/default/8.spi_device_alert_test.2982567443
/workspace/coverage/default/8.spi_device_bit_transfer.4146887450
/workspace/coverage/default/8.spi_device_byte_transfer.387740283
/workspace/coverage/default/8.spi_device_cfg_cmd.2754610384
/workspace/coverage/default/8.spi_device_csb_read.2063490447
/workspace/coverage/default/8.spi_device_dummy_item_extra_dly.3505106987
/workspace/coverage/default/8.spi_device_extreme_fifo_size.2663908891
/workspace/coverage/default/8.spi_device_fifo_full.3630548532
/workspace/coverage/default/8.spi_device_fifo_underflow_overflow.1546276546
/workspace/coverage/default/8.spi_device_flash_and_tpm.232758720
/workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1698821790
/workspace/coverage/default/8.spi_device_flash_mode.3203964288
/workspace/coverage/default/8.spi_device_intercept.2812352054
/workspace/coverage/default/8.spi_device_intr.1348267734
/workspace/coverage/default/8.spi_device_mailbox.456283142
/workspace/coverage/default/8.spi_device_mem_parity.3288396229
/workspace/coverage/default/8.spi_device_pass_addr_payload_swap.14310392
/workspace/coverage/default/8.spi_device_pass_cmd_filtering.2284187971
/workspace/coverage/default/8.spi_device_perf.2341404866
/workspace/coverage/default/8.spi_device_ram_cfg.3540205254
/workspace/coverage/default/8.spi_device_read_buffer_direct.1981165023
/workspace/coverage/default/8.spi_device_rx_async_fifo_reset.2070303046
/workspace/coverage/default/8.spi_device_rx_timeout.2546918640
/workspace/coverage/default/8.spi_device_smoke.2382075129
/workspace/coverage/default/8.spi_device_stress_all.1290973741
/workspace/coverage/default/8.spi_device_tpm_all.487710341
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2619948496
/workspace/coverage/default/8.spi_device_tpm_rw.2772829765
/workspace/coverage/default/8.spi_device_tpm_sts_read.513622292
/workspace/coverage/default/8.spi_device_tx_async_fifo_reset.2968969724
/workspace/coverage/default/8.spi_device_txrx.101144681
/workspace/coverage/default/8.spi_device_upload.1659376256
/workspace/coverage/default/9.spi_device_abort.2731670223
/workspace/coverage/default/9.spi_device_alert_test.821641827
/workspace/coverage/default/9.spi_device_bit_transfer.1471940413
/workspace/coverage/default/9.spi_device_byte_transfer.2156746305
/workspace/coverage/default/9.spi_device_cfg_cmd.320809108
/workspace/coverage/default/9.spi_device_csb_read.1944519875
/workspace/coverage/default/9.spi_device_dummy_item_extra_dly.2705495456
/workspace/coverage/default/9.spi_device_extreme_fifo_size.2058769538
/workspace/coverage/default/9.spi_device_fifo_full.3371289018
/workspace/coverage/default/9.spi_device_fifo_underflow_overflow.319455270
/workspace/coverage/default/9.spi_device_flash_all.1889113643
/workspace/coverage/default/9.spi_device_flash_and_tpm.2316415932
/workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3193043
/workspace/coverage/default/9.spi_device_flash_mode.990457302
/workspace/coverage/default/9.spi_device_intercept.3949085971
/workspace/coverage/default/9.spi_device_intr.2447377956
/workspace/coverage/default/9.spi_device_mailbox.1720782203
/workspace/coverage/default/9.spi_device_mem_parity.3149752840
/workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1036530029
/workspace/coverage/default/9.spi_device_pass_cmd_filtering.4147327708
/workspace/coverage/default/9.spi_device_perf.828761251
/workspace/coverage/default/9.spi_device_ram_cfg.4041348312
/workspace/coverage/default/9.spi_device_read_buffer_direct.1542109605
/workspace/coverage/default/9.spi_device_rx_async_fifo_reset.4109551377
/workspace/coverage/default/9.spi_device_rx_timeout.1216388284
/workspace/coverage/default/9.spi_device_smoke.1184766396
/workspace/coverage/default/9.spi_device_stress_all.1688650710
/workspace/coverage/default/9.spi_device_tpm_all.650139176
/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.159194540
/workspace/coverage/default/9.spi_device_tpm_rw.3053201930
/workspace/coverage/default/9.spi_device_tpm_sts_read.1694492895
/workspace/coverage/default/9.spi_device_tx_async_fifo_reset.2291298961
/workspace/coverage/default/9.spi_device_txrx.4242911622
/workspace/coverage/default/9.spi_device_upload.2735848976

---

Total test records in report: 1782

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tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/3.spi_device_ram_cfg.4059320836			Jan 21 07:53:42 PM PST 24	Jan 21 07:53:45 PM PST 24	45661598 ps
T1	/workspace/coverage/default/22.spi_device_bit_transfer.231188840			Jan 21 08:00:44 PM PST 24	Jan 21 08:00:49 PM PST 24	2331738351 ps
T2	/workspace/coverage/default/12.spi_device_mem_parity.1917084947			Jan 21 07:56:26 PM PST 24	Jan 21 07:56:28 PM PST 24	340141166 ps
T9	/workspace/coverage/default/25.spi_device_mailbox.3750962473			Jan 21 08:02:20 PM PST 24	Jan 21 08:02:58 PM PST 24	66779249725 ps
T3	/workspace/coverage/default/27.spi_device_bit_transfer.17861041			Jan 21 08:02:58 PM PST 24	Jan 21 08:03:28 PM PST 24	325769728 ps
T8	/workspace/coverage/default/27.spi_device_smoke.2826582169			Jan 21 08:02:49 PM PST 24	Jan 21 08:03:27 PM PST 24	112533885 ps
T12	/workspace/coverage/default/19.spi_device_extreme_fifo_size.2908971247			Jan 21 07:59:09 PM PST 24	Jan 21 08:13:59 PM PST 24	92280726426 ps
T78	/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.67150007			Jan 21 09:54:20 PM PST 24	Jan 21 09:54:37 PM PST 24	86541759 ps
T79	/workspace/coverage/cover_reg_top/37.spi_device_intr_test.1502493811			Jan 21 09:56:05 PM PST 24	Jan 21 09:56:08 PM PST 24	14443919 ps
T80	/workspace/coverage/cover_reg_top/14.spi_device_intr_test.662698470			Jan 21 09:55:41 PM PST 24	Jan 21 09:55:49 PM PST 24	38838154 ps
T81	/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4130428583			Jan 21 09:54:20 PM PST 24	Jan 21 09:54:37 PM PST 24	63412476 ps
T86	/workspace/coverage/cover_reg_top/5.spi_device_intr_test.97685210			Jan 21 10:34:58 PM PST 24	Jan 21 10:34:59 PM PST 24	44648795 ps
T87	/workspace/coverage/cover_reg_top/38.spi_device_intr_test.2676858865			Jan 21 09:56:05 PM PST 24	Jan 21 09:56:08 PM PST 24	29883745 ps
T85	/workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1074225889			Jan 21 09:55:39 PM PST 24	Jan 21 09:55:49 PM PST 24	928359247 ps
T82	/workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1309961512			Jan 21 09:54:59 PM PST 24	Jan 21 09:55:07 PM PST 24	120161792 ps
T228	/workspace/coverage/cover_reg_top/16.spi_device_intr_test.1328026366			Jan 21 09:55:35 PM PST 24	Jan 21 09:55:45 PM PST 24	14223775 ps
T83	/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2506660843			Jan 21 09:54:20 PM PST 24	Jan 21 09:54:41 PM PST 24	347197894 ps
T229	/workspace/coverage/cover_reg_top/46.spi_device_intr_test.2834041822			Jan 21 09:56:06 PM PST 24	Jan 21 09:56:10 PM PST 24	14200707 ps
T104	/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2132123707			Jan 21 09:55:43 PM PST 24	Jan 21 09:55:53 PM PST 24	143250363 ps
T230	/workspace/coverage/cover_reg_top/29.spi_device_intr_test.1733886005			Jan 21 09:55:53 PM PST 24	Jan 21 09:55:58 PM PST 24	30294338 ps
T105	/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3565629797			Jan 21 09:55:46 PM PST 24	Jan 21 09:55:54 PM PST 24	28524210 ps
T106	/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3833316864			Jan 21 09:54:19 PM PST 24	Jan 21 09:54:37 PM PST 24	29562148 ps
T180	/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2983142833			Jan 21 10:57:21 PM PST 24	Jan 21 10:57:27 PM PST 24	263125763 ps
T84	/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.66591742			Jan 21 09:54:48 PM PST 24	Jan 21 09:54:57 PM PST 24	152322308 ps
T184	/workspace/coverage/cover_reg_top/20.spi_device_intr_test.143383959			Jan 21 09:55:45 PM PST 24	Jan 21 09:55:52 PM PST 24	13378877 ps
T181	/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.202716834			Jan 21 10:23:40 PM PST 24	Jan 21 10:23:49 PM PST 24	68410831 ps
T185	/workspace/coverage/cover_reg_top/23.spi_device_intr_test.1112278045			Jan 21 10:55:51 PM PST 24	Jan 21 10:55:53 PM PST 24	15897371 ps
T182	/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4010778501			Jan 21 09:55:03 PM PST 24	Jan 21 09:55:09 PM PST 24	62909214 ps
T186	/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2456777598			Jan 21 09:54:20 PM PST 24	Jan 21 09:54:40 PM PST 24	165890181 ps
T189	/workspace/coverage/cover_reg_top/36.spi_device_intr_test.3628909956			Jan 21 09:56:09 PM PST 24	Jan 21 09:56:17 PM PST 24	24134282 ps
T134	/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.662217567			Jan 21 09:55:01 PM PST 24	Jan 21 09:55:08 PM PST 24	61647614 ps
T190	/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.908261287			Jan 21 09:54:44 PM PST 24	Jan 21 09:54:53 PM PST 24	20085927 ps
T191	/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2483613458			Jan 21 09:54:47 PM PST 24	Jan 21 09:54:55 PM PST 24	52444437 ps
T183	/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4246092276			Jan 21 10:14:45 PM PST 24	Jan 21 10:14:58 PM PST 24	95283456 ps
T207	/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2946733178			Jan 21 09:55:19 PM PST 24	Jan 21 09:55:34 PM PST 24	845600130 ps
T208	/workspace/coverage/cover_reg_top/22.spi_device_intr_test.3598079592			Jan 21 09:55:50 PM PST 24	Jan 21 09:55:55 PM PST 24	15867052 ps
T209	/workspace/coverage/cover_reg_top/10.spi_device_intr_test.1408024305			Jan 21 11:20:48 PM PST 24	Jan 21 11:20:57 PM PST 24	96594108 ps
T213	/workspace/coverage/cover_reg_top/35.spi_device_intr_test.3135652798			Jan 21 09:56:08 PM PST 24	Jan 21 09:56:12 PM PST 24	157861125 ps
T187	/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.829233734			Jan 21 09:54:35 PM PST 24	Jan 21 09:55:04 PM PST 24	2586184611 ps
T188	/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2719893643			Jan 21 11:12:33 PM PST 24	Jan 21 11:12:39 PM PST 24	731874252 ps
T216	/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3336494681			Jan 21 09:55:45 PM PST 24	Jan 21 09:55:52 PM PST 24	51968138 ps
T377	/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1057336455			Jan 21 09:54:12 PM PST 24	Jan 21 09:54:42 PM PST 24	205478788 ps
T135	/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3068818604			Jan 21 09:55:28 PM PST 24	Jan 21 09:55:47 PM PST 24	624910254 ps
T136	/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.476785099			Jan 21 09:55:46 PM PST 24	Jan 21 09:56:07 PM PST 24	2257818422 ps
T171	/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2892927587			Jan 21 09:55:30 PM PST 24	Jan 21 09:55:44 PM PST 24	104618037 ps
T172	/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1247086664			Jan 21 09:55:31 PM PST 24	Jan 21 09:55:45 PM PST 24	101592023 ps
T173	/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.38617636			Jan 21 10:24:28 PM PST 24	Jan 21 10:24:57 PM PST 24	1617919554 ps
T144	/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3578733127			Jan 21 09:54:49 PM PST 24	Jan 21 09:54:56 PM PST 24	95546171 ps
T174	/workspace/coverage/cover_reg_top/13.spi_device_intr_test.1516223846			Jan 21 09:55:30 PM PST 24	Jan 21 09:55:42 PM PST 24	14458145 ps
T175	/workspace/coverage/cover_reg_top/1.spi_device_intr_test.3163248951			Jan 21 09:54:20 PM PST 24	Jan 21 09:54:36 PM PST 24	11982226 ps
T139	/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1370910887			Jan 21 09:55:51 PM PST 24	Jan 21 09:56:00 PM PST 24	96184024 ps
T140	/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1969930335			Jan 21 09:54:48 PM PST 24	Jan 21 09:54:59 PM PST 24	323608957 ps
T215	/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1480776193			Jan 21 09:55:10 PM PST 24	Jan 21 09:55:17 PM PST 24	68207292 ps
T138	/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3088616462			Jan 21 09:54:37 PM PST 24	Jan 21 09:55:03 PM PST 24	1339166658 ps
T378	/workspace/coverage/cover_reg_top/24.spi_device_intr_test.2850236836			Jan 21 09:55:51 PM PST 24	Jan 21 09:55:56 PM PST 24	39713309 ps
T379	/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.324090515			Jan 21 09:55:44 PM PST 24	Jan 21 09:55:53 PM PST 24	23730410 ps
T210	/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2688846369			Jan 21 10:42:07 PM PST 24	Jan 21 10:42:12 PM PST 24	851422179 ps
T214	/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1953966864			Jan 21 09:55:44 PM PST 24	Jan 21 09:55:53 PM PST 24	146723387 ps
T169	/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2993111437			Jan 21 10:35:41 PM PST 24	Jan 21 10:35:58 PM PST 24	699466126 ps
T245	/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.657940121			Jan 21 09:55:35 PM PST 24	Jan 21 09:55:52 PM PST 24	453298809 ps
T179	/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1432602856			Jan 21 09:54:49 PM PST 24	Jan 21 09:55:02 PM PST 24	545436862 ps
T380	/workspace/coverage/cover_reg_top/26.spi_device_intr_test.3625713688			Jan 21 11:03:53 PM PST 24	Jan 21 11:04:01 PM PST 24	61870866 ps
T146	/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.862084369			Jan 21 09:54:41 PM PST 24	Jan 21 09:54:51 PM PST 24	76712830 ps
T176	/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.359561980			Jan 21 09:55:43 PM PST 24	Jan 21 09:56:08 PM PST 24	775345124 ps
T381	/workspace/coverage/cover_reg_top/25.spi_device_intr_test.2868330907			Jan 21 09:55:53 PM PST 24	Jan 21 09:55:58 PM PST 24	13057665 ps
T178	/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1454010679			Jan 21 09:55:26 PM PST 24	Jan 21 09:55:50 PM PST 24	872307320 ps
T382	/workspace/coverage/cover_reg_top/15.spi_device_intr_test.4096623825			Jan 21 10:23:48 PM PST 24	Jan 21 10:23:53 PM PST 24	26086792 ps
T383	/workspace/coverage/cover_reg_top/12.spi_device_intr_test.4091848329			Jan 21 09:55:29 PM PST 24	Jan 21 09:55:41 PM PST 24	14619968 ps
T384	/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1328960832			Jan 21 09:54:35 PM PST 24	Jan 21 09:54:49 PM PST 24	92097135 ps
T192	/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.853638295			Jan 21 09:55:44 PM PST 24	Jan 21 09:55:52 PM PST 24	167575323 ps
T193	/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3916670638			Jan 21 09:54:21 PM PST 24	Jan 21 09:54:54 PM PST 24	1033228813 ps
T170	/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3801479421			Jan 21 09:55:01 PM PST 24	Jan 21 09:55:31 PM PST 24	3446026131 ps
T385	/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1440630848			Jan 21 09:55:01 PM PST 24	Jan 21 09:55:09 PM PST 24	427608427 ps
T386	/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2735160713			Jan 21 09:54:17 PM PST 24	Jan 21 09:54:48 PM PST 24	2793412051 ps
T211	/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.557022532			Jan 21 09:55:35 PM PST 24	Jan 21 09:55:47 PM PST 24	628677598 ps
T387	/workspace/coverage/cover_reg_top/6.spi_device_intr_test.3916617628			Jan 21 09:55:00 PM PST 24	Jan 21 09:55:06 PM PST 24	241627363 ps
T388	/workspace/coverage/cover_reg_top/18.spi_device_intr_test.2426687670			Jan 21 09:55:40 PM PST 24	Jan 21 09:55:48 PM PST 24	13143674 ps
T141	/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3687053282			Jan 21 09:55:41 PM PST 24	Jan 21 09:55:53 PM PST 24	362875789 ps
T177	/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3783183532			Jan 21 09:54:20 PM PST 24	Jan 21 09:54:42 PM PST 24	154116148 ps
T389	/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3619102004			Jan 21 09:54:36 PM PST 24	Jan 21 09:54:51 PM PST 24	521253198 ps
T390	/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3625731874			Jan 21 09:54:48 PM PST 24	Jan 21 09:55:09 PM PST 24	766921711 ps
T212	/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1043197184			Jan 21 11:10:14 PM PST 24	Jan 21 11:10:19 PM PST 24	44005614 ps
T391	/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3775942759			Jan 21 10:30:40 PM PST 24	Jan 21 10:30:53 PM PST 24	442813859 ps
T194	/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.635299100			Jan 21 09:54:15 PM PST 24	Jan 21 09:54:37 PM PST 24	54081561 ps
T392	/workspace/coverage/cover_reg_top/0.spi_device_intr_test.3987155063			Jan 21 09:54:16 PM PST 24	Jan 21 09:54:34 PM PST 24	42339097 ps
T142	/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4021793935			Jan 21 10:18:04 PM PST 24	Jan 21 10:18:18 PM PST 24	51355477 ps
T393	/workspace/coverage/cover_reg_top/39.spi_device_intr_test.558293534			Jan 21 09:56:06 PM PST 24	Jan 21 09:56:09 PM PST 24	19692804 ps
T195	/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2206919976			Jan 21 09:54:21 PM PST 24	Jan 21 09:54:38 PM PST 24	83840315 ps
T394	/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1320922378			Jan 21 09:55:31 PM PST 24	Jan 21 09:55:44 PM PST 24	420701890 ps
T196	/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3557166906			Jan 21 11:15:23 PM PST 24	Jan 21 11:15:27 PM PST 24	40400578 ps
T395	/workspace/coverage/cover_reg_top/11.spi_device_intr_test.3607146884			Jan 21 09:55:30 PM PST 24	Jan 21 09:55:42 PM PST 24	15159418 ps
T145	/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.200397131			Jan 21 10:29:46 PM PST 24	Jan 21 10:29:51 PM PST 24	65905214 ps
T396	/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.821273054			Jan 21 09:55:51 PM PST 24	Jan 21 09:55:58 PM PST 24	82295406 ps
T143	/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.921185772			Jan 21 09:55:29 PM PST 24	Jan 21 09:55:44 PM PST 24	181400747 ps
T397	/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1303203789			Jan 21 09:54:24 PM PST 24	Jan 21 09:55:08 PM PST 24	3981151398 ps
T398	/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4164710340			Jan 21 09:55:36 PM PST 24	Jan 21 09:55:48 PM PST 24	256463360 ps
T240	/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2624104223			Jan 21 10:30:54 PM PST 24	Jan 21 10:31:04 PM PST 24	113780566 ps
T399	/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2405927684			Jan 21 09:55:36 PM PST 24	Jan 21 09:55:47 PM PST 24	90314478 ps
T400	/workspace/coverage/cover_reg_top/31.spi_device_intr_test.3178228316			Jan 21 11:08:40 PM PST 24	Jan 21 11:08:42 PM PST 24	43101274 ps
T401	/workspace/coverage/cover_reg_top/43.spi_device_intr_test.2590906910			Jan 21 09:56:06 PM PST 24	Jan 21 09:56:10 PM PST 24	32977654 ps
T402	/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2624203680			Jan 21 09:55:10 PM PST 24	Jan 21 09:55:22 PM PST 24	219809628 ps
T403	/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1545828100			Jan 21 10:38:22 PM PST 24	Jan 21 10:38:26 PM PST 24	289472962 ps
T404	/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.375568616			Jan 21 09:54:39 PM PST 24	Jan 21 09:54:51 PM PST 24	106922690 ps
T405	/workspace/coverage/cover_reg_top/42.spi_device_intr_test.2747537735			Jan 21 09:56:08 PM PST 24	Jan 21 09:56:12 PM PST 24	44715482 ps
T406	/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.213373167			Jan 21 09:54:41 PM PST 24	Jan 21 09:55:15 PM PST 24	2266399692 ps
T407	/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1855896			Jan 21 09:54:36 PM PST 24	Jan 21 09:54:49 PM PST 24	50655910 ps
T408	/workspace/coverage/cover_reg_top/41.spi_device_intr_test.3452236453			Jan 21 09:56:05 PM PST 24	Jan 21 09:56:08 PM PST 24	13151125 ps
T409	/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1334360523			Jan 21 09:55:28 PM PST 24	Jan 21 09:55:41 PM PST 24	182094433 ps
T410	/workspace/coverage/cover_reg_top/45.spi_device_intr_test.340490574			Jan 21 09:56:08 PM PST 24	Jan 21 09:56:12 PM PST 24	15397938 ps
T411	/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1525610740			Jan 21 10:24:17 PM PST 24	Jan 21 10:24:37 PM PST 24	257455623 ps
T412	/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3074653055			Jan 21 09:55:35 PM PST 24	Jan 21 09:55:46 PM PST 24	42796744 ps
T413	/workspace/coverage/cover_reg_top/28.spi_device_intr_test.2313856235			Jan 21 09:55:53 PM PST 24	Jan 21 09:55:58 PM PST 24	66449738 ps
T414	/workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4217560174			Jan 21 09:54:20 PM PST 24	Jan 21 09:54:38 PM PST 24	457593103 ps
T415	/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.338397950			Jan 21 09:55:37 PM PST 24	Jan 21 09:55:48 PM PST 24	277132057 ps
T416	/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4225546696			Jan 21 09:55:51 PM PST 24	Jan 21 09:56:00 PM PST 24	169865638 ps
T417	/workspace/coverage/cover_reg_top/48.spi_device_intr_test.1299187516			Jan 21 09:56:06 PM PST 24	Jan 21 09:56:09 PM PST 24	37166122 ps
T418	/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1836514667			Jan 21 09:54:41 PM PST 24	Jan 21 09:54:55 PM PST 24	224152480 ps
T244	/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1066234472			Jan 21 09:55:12 PM PST 24	Jan 21 09:55:27 PM PST 24	237342106 ps
T419	/workspace/coverage/cover_reg_top/3.spi_device_intr_test.3787905446			Jan 21 09:54:38 PM PST 24	Jan 21 09:54:49 PM PST 24	45660619 ps
T420	/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3480102570			Jan 21 09:55:12 PM PST 24	Jan 21 09:55:21 PM PST 24	19806194 ps
T421	/workspace/coverage/cover_reg_top/4.spi_device_intr_test.2394895458			Jan 21 09:54:49 PM PST 24	Jan 21 09:54:56 PM PST 24	17624414 ps
T422	/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2486261409			Jan 21 09:55:46 PM PST 24	Jan 21 09:55:55 PM PST 24	136724710 ps
T423	/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.504761102			Jan 21 09:55:09 PM PST 24	Jan 21 09:55:21 PM PST 24	924444659 ps
T424	/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1753478382			Jan 21 09:55:00 PM PST 24	Jan 21 09:55:07 PM PST 24	62989602 ps
T425	/workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1297345731			Jan 21 09:54:16 PM PST 24	Jan 21 09:54:37 PM PST 24	66543352 ps
T242	/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.608021002			Jan 21 09:54:29 PM PST 24	Jan 21 09:55:06 PM PST 24	3440730082 ps
T426	/workspace/coverage/cover_reg_top/21.spi_device_intr_test.4194161103			Jan 21 10:58:00 PM PST 24	Jan 21 10:58:03 PM PST 24	26175485 ps
T427	/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.597285142			Jan 21 09:54:14 PM PST 24	Jan 21 09:54:33 PM PST 24	144575896 ps
T428	/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2889202040			Jan 21 09:55:32 PM PST 24	Jan 21 09:55:44 PM PST 24	38377443 ps
T429	/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.598071670			Jan 21 09:55:34 PM PST 24	Jan 21 09:55:46 PM PST 24	448303317 ps
T430	/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.701919141			Jan 21 09:55:27 PM PST 24	Jan 21 09:55:43 PM PST 24	441943398 ps
T431	/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4109492060			Jan 21 10:57:22 PM PST 24	Jan 21 10:57:31 PM PST 24	124883689 ps
T432	/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3368986987			Jan 21 09:55:30 PM PST 24	Jan 21 09:55:47 PM PST 24	188278572 ps
T433	/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4007755316			Jan 21 09:54:24 PM PST 24	Jan 21 09:54:44 PM PST 24	348191442 ps
T434	/workspace/coverage/cover_reg_top/44.spi_device_intr_test.2004041903			Jan 21 09:56:13 PM PST 24	Jan 21 09:56:23 PM PST 24	13969615 ps
T435	/workspace/coverage/cover_reg_top/30.spi_device_intr_test.4268281799			Jan 21 09:55:52 PM PST 24	Jan 21 09:55:57 PM PST 24	183356553 ps
T436	/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2368005454			Jan 21 09:55:51 PM PST 24	Jan 21 09:55:57 PM PST 24	135321321 ps
T437	/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1626887194			Jan 21 09:54:42 PM PST 24	Jan 21 09:55:16 PM PST 24	699956570 ps
T438	/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.81900995			Jan 21 09:55:12 PM PST 24	Jan 21 09:55:25 PM PST 24	59940192 ps
T439	/workspace/coverage/cover_reg_top/9.spi_device_intr_test.3472940953			Jan 21 09:55:11 PM PST 24	Jan 21 09:55:19 PM PST 24	25374515 ps
T440	/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1530678092			Jan 21 09:54:27 PM PST 24	Jan 21 09:54:54 PM PST 24	243734752 ps
T441	/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4079876717			Jan 21 09:55:34 PM PST 24	Jan 21 09:55:45 PM PST 24	35605902 ps
T442	/workspace/coverage/cover_reg_top/40.spi_device_intr_test.564477677			Jan 21 09:56:04 PM PST 24	Jan 21 09:56:08 PM PST 24	50781104 ps
T443	/workspace/coverage/cover_reg_top/7.spi_device_intr_test.328301666			Jan 21 09:54:58 PM PST 24	Jan 21 09:55:00 PM PST 24	15401957 ps
T444	/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3065370249			Jan 21 09:54:28 PM PST 24	Jan 21 09:54:46 PM PST 24	822161447 ps
T445	/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.828260315			Jan 21 09:55:45 PM PST 24	Jan 21 09:55:55 PM PST 24	278474678 ps
T446	/workspace/coverage/cover_reg_top/17.spi_device_intr_test.3165535478			Jan 21 09:55:45 PM PST 24	Jan 21 09:55:52 PM PST 24	14324132 ps
T447	/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3835358141			Jan 21 09:55:12 PM PST 24	Jan 21 09:55:26 PM PST 24	168665473 ps
T448	/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2727449692			Jan 21 10:22:25 PM PST 24	Jan 21 10:22:36 PM PST 24	54623551 ps
T449	/workspace/coverage/cover_reg_top/2.spi_device_intr_test.2549236575			Jan 21 09:54:27 PM PST 24	Jan 21 09:54:40 PM PST 24	47765101 ps
T450	/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.717308325			Jan 21 09:54:36 PM PST 24	Jan 21 09:54:50 PM PST 24	294845362 ps
T451	/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.557964347			Jan 21 09:54:37 PM PST 24	Jan 21 09:55:02 PM PST 24	719085528 ps
T452	/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2468116329			Jan 21 09:55:44 PM PST 24	Jan 21 09:55:55 PM PST 24	1013723778 ps
T453	/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.544357933			Jan 21 09:55:14 PM PST 24	Jan 21 09:55:27 PM PST 24	20469778 ps
T454	/workspace/coverage/cover_reg_top/32.spi_device_intr_test.3216056519			Jan 21 09:55:51 PM PST 24	Jan 21 09:55:56 PM PST 24	45262190 ps
T455	/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3785828091			Jan 21 09:55:32 PM PST 24	Jan 21 09:55:44 PM PST 24	91342598 ps
T456	/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.268299621			Jan 21 09:54:14 PM PST 24	Jan 21 09:54:57 PM PST 24	837365171 ps
T241	/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.142812907			Jan 21 09:55:36 PM PST 24	Jan 21 09:56:02 PM PST 24	1122432416 ps
T457	/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1642540526			Jan 21 09:55:35 PM PST 24	Jan 21 09:55:47 PM PST 24	162595928 ps
T458	/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4124952312			Jan 21 09:55:43 PM PST 24	Jan 21 09:55:52 PM PST 24	85770655 ps
T459	/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1072278109			Jan 21 09:54:30 PM PST 24	Jan 21 09:54:45 PM PST 24	16019399 ps
T243	/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.973160092			Jan 21 09:55:33 PM PST 24	Jan 21 09:55:56 PM PST 24	413916746 ps
T460	/workspace/coverage/cover_reg_top/47.spi_device_intr_test.2129068466			Jan 21 09:56:09 PM PST 24	Jan 21 09:56:13 PM PST 24	41621891 ps
T461	/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4285448402			Jan 21 09:55:47 PM PST 24	Jan 21 09:55:55 PM PST 24	276862198 ps
T462	/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1785088052			Jan 21 09:55:30 PM PST 24	Jan 21 09:55:44 PM PST 24	50078660 ps
T463	/workspace/coverage/cover_reg_top/33.spi_device_intr_test.3364202280			Jan 21 09:56:01 PM PST 24	Jan 21 09:56:04 PM PST 24	15226170 ps
T464	/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2895358742			Jan 21 09:55:00 PM PST 24	Jan 21 09:55:11 PM PST 24	931191415 ps
T465	/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3951637213			Jan 21 09:54:52 PM PST 24	Jan 21 09:54:59 PM PST 24	177870907 ps
T466	/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.813515927			Jan 21 09:55:03 PM PST 24	Jan 21 09:55:09 PM PST 24	79448006 ps
T467	/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2114208978			Jan 21 10:35:03 PM PST 24	Jan 21 10:35:15 PM PST 24	661853484 ps
T468	/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.47321130			Jan 21 09:54:59 PM PST 24	Jan 21 09:55:08 PM PST 24	157984390 ps
T469	/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1289554681			Jan 21 09:55:36 PM PST 24	Jan 21 09:55:47 PM PST 24	35663355 ps
T470	/workspace/coverage/cover_reg_top/34.spi_device_intr_test.1397981374			Jan 21 09:56:05 PM PST 24	Jan 21 09:56:08 PM PST 24	13446384 ps
T471	/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4035835543			Jan 21 09:54:19 PM PST 24	Jan 21 09:54:56 PM PST 24	1021145526 ps
T472	/workspace/coverage/cover_reg_top/49.spi_device_intr_test.1108137393			Jan 21 09:56:07 PM PST 24	Jan 21 09:56:11 PM PST 24	42689769 ps
T473	/workspace/coverage/cover_reg_top/27.spi_device_intr_test.3779336153			Jan 21 09:55:50 PM PST 24	Jan 21 09:55:55 PM PST 24	26332518 ps
T474	/workspace/coverage/cover_reg_top/8.spi_device_intr_test.702748308			Jan 21 09:55:13 PM PST 24	Jan 21 09:55:23 PM PST 24	17488279 ps
T475	/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3758581355			Jan 21 09:55:27 PM PST 24	Jan 21 09:55:41 PM PST 24	43397074 ps
T476	/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4110982043			Jan 21 09:54:34 PM PST 24	Jan 21 09:54:47 PM PST 24	43325787 ps
T477	/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2772002269			Jan 21 09:55:44 PM PST 24	Jan 21 09:56:14 PM PST 24	997353101 ps
T478	/workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2102688938			Jan 21 09:54:24 PM PST 24	Jan 21 09:54:40 PM PST 24	352549947 ps
T479	/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1313537311			Jan 21 09:54:42 PM PST 24	Jan 21 09:55:17 PM PST 24	6166823756 ps
T13	/workspace/coverage/default/31.spi_device_perf.1448583667			Jan 21 08:09:02 PM PST 24	Jan 21 08:14:15 PM PST 24	12357714907 ps
T14	/workspace/coverage/default/11.spi_device_perf.3264458573			Jan 21 07:55:59 PM PST 24	Jan 21 08:25:22 PM PST 24	24646593415 ps
T15	/workspace/coverage/default/48.spi_device_cfg_cmd.3501562353			Jan 21 08:16:30 PM PST 24	Jan 21 08:16:35 PM PST 24	247416025 ps
T42	/workspace/coverage/default/15.spi_device_ram_cfg.2001376216			Jan 21 07:57:43 PM PST 24	Jan 21 07:57:45 PM PST 24	16469196 ps
T10	/workspace/coverage/default/49.spi_device_read_buffer_direct.1054078421			Jan 21 09:31:43 PM PST 24	Jan 21 09:32:16 PM PST 24	1026633272 ps
T16	/workspace/coverage/default/35.spi_device_smoke.3503974487			Jan 21 08:10:32 PM PST 24	Jan 21 08:10:37 PM PST 24	115750484 ps
T40	/workspace/coverage/default/43.spi_device_rx_timeout.1547553959			Jan 21 08:14:03 PM PST 24	Jan 21 08:14:10 PM PST 24	8733167838 ps
T41	/workspace/coverage/default/8.spi_device_rx_async_fifo_reset.2070303046			Jan 21 07:55:02 PM PST 24	Jan 21 07:55:04 PM PST 24	43476493 ps
T17	/workspace/coverage/default/24.spi_device_pass_cmd_filtering.4106577060			Jan 21 08:01:44 PM PST 24	Jan 21 08:01:50 PM PST 24	226147143 ps
T5	/workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.475251040			Jan 21 08:12:47 PM PST 24	Jan 21 08:13:59 PM PST 24	14922674091 ps
T50	/workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3903988730			Jan 21 07:56:09 PM PST 24	Jan 21 07:56:15 PM PST 24	916359581 ps
T11	/workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3723078509			Jan 21 08:14:41 PM PST 24	Jan 21 08:14:54 PM PST 24	589851018 ps
T49	/workspace/coverage/default/37.spi_device_extreme_fifo_size.3826836212			Jan 21 08:11:30 PM PST 24	Jan 21 08:55:33 PM PST 24	292927546715 ps
T51	/workspace/coverage/default/5.spi_device_fifo_full.454583272			Jan 21 07:54:13 PM PST 24	Jan 21 08:17:31 PM PST 24	23541147245 ps
T52	/workspace/coverage/default/39.spi_device_tpm_all.129991882			Jan 21 09:25:16 PM PST 24	Jan 21 09:26:20 PM PST 24	37913617556 ps
T53	/workspace/coverage/default/40.spi_device_txrx.481663900			Jan 21 08:12:45 PM PST 24	Jan 21 08:16:26 PM PST 24	36090206150 ps
T19	/workspace/coverage/default/44.spi_device_upload.1754713914			Jan 21 08:14:52 PM PST 24	Jan 21 08:15:06 PM PST 24	3215615508 ps
T6	/workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.798798902			Jan 21 08:01:59 PM PST 24	Jan 21 08:05:45 PM PST 24	26476387822 ps
T33	/workspace/coverage/default/19.spi_device_intr.3288735231			Jan 21 07:59:10 PM PST 24	Jan 21 07:59:22 PM PST 24	15000548449 ps
T7	/workspace/coverage/default/28.spi_device_flash_all.2936443735			Jan 21 08:03:51 PM PST 24	Jan 21 08:05:27 PM PST 24	4438171134 ps
T137	/workspace/coverage/default/33.spi_device_cfg_cmd.156843268			Jan 21 08:10:32 PM PST 24	Jan 21 08:10:39 PM PST 24	111407897 ps
T99	/workspace/coverage/default/18.spi_device_csb_read.2433492697			Jan 21 07:58:52 PM PST 24	Jan 21 07:58:54 PM PST 24	16485101 ps
T100	/workspace/coverage/default/16.spi_device_dummy_item_extra_dly.3844427143			Jan 21 07:58:09 PM PST 24	Jan 21 08:04:18 PM PST 24	25914011783 ps
T94	/workspace/coverage/default/36.spi_device_tx_async_fifo_reset.1896575094			Jan 21 08:11:16 PM PST 24	Jan 21 08:11:25 PM PST 24	44682102 ps
T132	/workspace/coverage/default/25.spi_device_rx_timeout.1589537101			Jan 21 08:02:12 PM PST 24	Jan 21 08:02:20 PM PST 24	2373717661 ps
T125	/workspace/coverage/default/28.spi_device_intr.3458904979			Jan 21 08:03:23 PM PST 24	Jan 21 08:04:05 PM PST 24	13232402545 ps
T90	/workspace/coverage/default/27.spi_device_abort.1772911131			Jan 21 08:03:21 PM PST 24	Jan 21 08:03:31 PM PST 24	41345440 ps
T43	/workspace/coverage/default/43.spi_device_read_buffer_direct.3807489108			Jan 21 08:14:13 PM PST 24	Jan 21 08:14:19 PM PST 24	388169292 ps
T23	/workspace/coverage/default/26.spi_device_mailbox.1557288672			Jan 21 08:02:47 PM PST 24	Jan 21 08:03:32 PM PST 24	787176556 ps
T97	/workspace/coverage/default/23.spi_device_rx_async_fifo_reset.165924984			Jan 21 08:01:03 PM PST 24	Jan 21 08:01:11 PM PST 24	28477585 ps
T126	/workspace/coverage/default/45.spi_device_intr.2426245460			Jan 21 08:14:53 PM PST 24	Jan 21 08:17:13 PM PST 24	30276473128 ps
T120	/workspace/coverage/default/43.spi_device_tpm_all.1008403874			Jan 21 08:14:00 PM PST 24	Jan 21 08:14:42 PM PST 24	8512777082 ps
T46	/workspace/coverage/default/49.spi_device_flash_mode.972596113			Jan 21 08:16:49 PM PST 24	Jan 21 08:16:56 PM PST 24	656922022 ps
T95	/workspace/coverage/default/10.spi_device_tx_async_fifo_reset.3098043350			Jan 21 07:55:54 PM PST 24	Jan 21 07:55:56 PM PST 24	17608534 ps
T24	/workspace/coverage/default/38.spi_device_intercept.2445617426			Jan 21 08:12:11 PM PST 24	Jan 21 08:12:17 PM PST 24	234755228 ps
T121	/workspace/coverage/default/49.spi_device_tpm_all.2589762183			Jan 21 08:16:43 PM PST 24	Jan 21 08:18:24 PM PST 24	28164059360 ps
T122	/workspace/coverage/default/28.spi_device_tpm_all.2017723143			Jan 21 08:03:28 PM PST 24	Jan 21 08:03:40 PM PST 24	389114174 ps
T480	/workspace/coverage/default/8.spi_device_intercept.2812352054			Jan 21 07:55:07 PM PST 24	Jan 21 07:55:11 PM PST 24	154709638 ps
T247	/workspace/coverage/default/39.spi_device_fifo_full.1773831518			Jan 21 08:44:48 PM PST 24	Jan 21 08:55:18 PM PST 24	60021454399 ps
T220	/workspace/coverage/default/23.spi_device_extreme_fifo_size.977244519			Jan 21 08:32:52 PM PST 24	Jan 21 08:48:01 PM PST 24	841140768154 ps
T44	/workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3071352667			Jan 21 10:05:23 PM PST 24	Jan 21 10:07:54 PM PST 24	33813396845 ps
T101	/workspace/coverage/default/34.spi_device_alert_test.299624592			Jan 21 08:10:33 PM PST 24	Jan 21 08:10:38 PM PST 24	89545210 ps
T18	/workspace/coverage/default/0.spi_device_flash_all.381179849			Jan 21 07:53:03 PM PST 24	Jan 21 07:53:58 PM PST 24	12922903532 ps
T34	/workspace/coverage/default/10.spi_device_intercept.1270560770			Jan 21 07:55:55 PM PST 24	Jan 21 07:55:59 PM PST 24	201461080 ps
T93	/workspace/coverage/default/29.spi_device_abort.2961569861			Jan 21 08:04:44 PM PST 24	Jan 21 08:04:46 PM PST 24	34610463 ps
T35	/workspace/coverage/default/40.spi_device_smoke.2800673235			Jan 21 08:12:44 PM PST 24	Jan 21 08:12:46 PM PST 24	33294321 ps
T36	/workspace/coverage/default/3.spi_device_intr.1850770048			Jan 21 08:58:41 PM PST 24	Jan 21 08:59:51 PM PST 24	9331884162 ps
T37	/workspace/coverage/default/31.spi_device_bit_transfer.1190489732			Jan 21 08:09:02 PM PST 24	Jan 21 08:09:09 PM PST 24	171133350 ps
T107	/workspace/coverage/default/8.spi_device_ram_cfg.3540205254			Jan 21 07:54:59 PM PST 24	Jan 21 07:55:01 PM PST 24	46090352 ps
T38	/workspace/coverage/default/24.spi_device_intr.1972163412			Jan 21 08:01:25 PM PST 24	Jan 21 08:03:42 PM PST 24	37531313548 ps
T39	/workspace/coverage/default/10.spi_device_tpm_all.2676631538			Jan 21 07:55:44 PM PST 24	Jan 21 07:56:11 PM PST 24	3331607034 ps
T25	/workspace/coverage/default/13.spi_device_mailbox.1521722505			Jan 21 07:57:06 PM PST 24	Jan 21 07:57:24 PM PST 24	9747709764 ps
T123	/workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1462215869			Jan 21 08:12:10 PM PST 24	Jan 21 08:12:35 PM PST 24	18805172348 ps
T481	/workspace/coverage/default/12.spi_device_perf.1344252597			Jan 21 07:56:29 PM PST 24	Jan 21 08:04:29 PM PST 24	16035147511 ps
T482	/workspace/coverage/default/30.spi_device_byte_transfer.2119408847			Jan 21 08:08:40 PM PST 24	Jan 21 08:08:44 PM PST 24	376781405 ps
T267	/workspace/coverage/default/45.spi_device_upload.1156753659			Jan 21 08:35:16 PM PST 24	Jan 21 08:35:20 PM PST 24	1035771115 ps
T129	/workspace/coverage/default/6.spi_device_tpm_sts_read.3093576967			Jan 21 07:54:27 PM PST 24	Jan 21 07:54:29 PM PST 24	15196635 ps
T246	/workspace/coverage/default/3.spi_device_smoke.3768136214			Jan 21 07:53:41 PM PST 24	Jan 21 07:53:44 PM PST 24	26881510 ps
T483	/workspace/coverage/default/46.spi_device_csb_read.4261102721			Jan 21 08:15:16 PM PST 24	Jan 21 08:15:24 PM PST 24	41085338 ps
T272	/workspace/coverage/default/27.spi_device_upload.3684496646			Jan 21 08:03:19 PM PST 24	Jan 21 08:03:43 PM PST 24	3997485703 ps
T124	/workspace/coverage/default/20.spi_device_tpm_all.1452651042			Jan 21 07:59:50 PM PST 24	Jan 21 08:00:42 PM PST 24	11393242538 ps
T484	/workspace/coverage/default/21.spi_device_smoke.1172517398			Jan 21 08:00:02 PM PST 24	Jan 21 08:00:08 PM PST 24	36256667 ps
T98	/workspace/coverage/default/26.spi_device_rx_async_fifo_reset.1918211291			Jan 21 08:02:41 PM PST 24	Jan 21 08:02:44 PM PST 24	149709839 ps
T133	/workspace/coverage/default/26.spi_device_rx_timeout.3285109861			Jan 21 08:02:31 PM PST 24	Jan 21 08:02:37 PM PST 24	570479131 ps
T130	/workspace/coverage/default/37.spi_device_read_buffer_direct.3366162872			Jan 21 08:11:50 PM PST 24	Jan 21 08:11:59 PM PST 24	250260134 ps
T222	/workspace/coverage/default/20.spi_device_intr.2083080555			Jan 21 07:59:45 PM PST 24	Jan 21 08:00:31 PM PST 24	30511455734 ps
T260	/workspace/coverage/default/42.spi_device_mailbox.1104638029			Jan 21 08:13:51 PM PST 24	Jan 21 08:14:04 PM PST 24	1449742580 ps
T147	/workspace/coverage/default/2.spi_device_rx_async_fifo_reset.13716545			Jan 21 07:53:36 PM PST 24	Jan 21 07:53:42 PM PST 24	45874084 ps