Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

Group : spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	16	0	16	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_bit_order	2	0	2	100.00	100	1	1	2
cp_cpha	2	0	2	100.00	100	1	1	2
cp_cpol	2	0	2	100.00	100	1	1	2
cp_rx_order	2	0	2	100.00	100	1	1	2
rx_order	2	0	2	100.00	100	1	1	2
tx_order	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::bit_order_clk_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_bit_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bit_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2964062

1

T1

26

T3

52

T12

763

auto[1]

2720764

1

T1

59

T3

40

T8

12

---

Summary for Variable cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpha

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2815209

1

T1

30

T3

60

T12

2578

auto[1]

2869617

1

T1

55

T3

32

T8

12

---

Summary for Variable cp_cpol

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_cpol

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2861170

1

T1

40

T3

66

T12

1815

auto[1]

2823656

1

T1

45

T3

26

T8

12

---

Summary for Variable cp_rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2686473

1

T1

50

T3

53

T8

12

auto[1]

2998353

1

T1

35

T3

39

T12

1815

---

Summary for Variable rx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2686473

1

T1

50

T3

53

T8

12

auto[1]

2998353

1

T1

35

T3

39

T12

1815

---

Summary for Variable tx_order

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for tx_order

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2964062

1

T1

26

T3

52

T12

763

auto[1]

2720764

1

T1

59

T3

40

T8

12

---

Summary for Cross cr_all

Samples crossed: tx_order rx_order cp_cpol cp_cpha

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

tx_order

rx_order

cp_cpol

cp_cpha

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

279465

1

T3

30

T37

6

T246

3

auto[0]

auto[0]

auto[0]

auto[1]

398425

1

T1

7

T14

4968

T247

5448

auto[0]

auto[0]

auto[1]

auto[0]

427503

1

T12

763

T51

10806

T53

8388

auto[0]

auto[0]

auto[1]

auto[1]

352965

1

T1

5

T3

1

T35

6

auto[0]

auto[1]

auto[0]

auto[0]

439502

1

T1

4

T3

4

T51

6757

auto[0]

auto[1]

auto[0]

auto[1]

385435

1

T1

5

T3

3

T13

2638

auto[0]

auto[1]

auto[1]

auto[0]

435205

1

T3

12

T16

3

T49

1241

auto[0]

auto[1]

auto[1]

auto[1]

245562

1

T1

5

T3

2

T53

1985

auto[1]

auto[0]

auto[0]

auto[0]

262774

1

T1

10

T3

8

T38

5006

auto[1]

auto[0]

auto[0]

auto[1]

373690

1

T1

8

T3

8

T94

1

auto[1]

auto[0]

auto[1]

auto[0]

271822

1

T1

10

T3

6

T13

7544

auto[1]

auto[0]

auto[1]

auto[1]

319829

1

T1

10

T8

12

T100

1115

auto[1]

auto[1]

auto[0]

auto[0]

387279

1

T1

6

T12

1815

T16

10

auto[1]

auto[1]

auto[0]

auto[1]

334600

1

T3

13

T33

304

T222

2353

auto[1]

auto[1]

auto[1]

auto[0]

311659

1

T14

9843

T100

8581

T132

116

auto[1]

auto[1]

auto[1]

auto[1]

459111

1

T1

15

T3

5

T41

12