Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	44455	1			T15	20		T17	2		T5	13
auto[SpiFlashAddrCfg]	9294	1			T5	1		T11	4		T19	6
auto[SpiFlashAddr3b]	11134	1			T9	8		T17	2		T5	9
auto[SpiFlashAddr4b]	9419	1			T9	6		T5	4		T11	14

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41966

1

T9

14

T15

20

T17

4

auto[1]

32336

1

T5

13

T11

26

T6

70

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39471

1

T9

14

T15

20

T17

2

auto[1]

34831

1

T17

2

T5

13

T11

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	49939	1			T15	20		T5	18		T11	6
values[1]	1339	1			T6	4		T7	7		T44	12
values[2]	1763	1			T5	3		T11	2		T6	6
values[3]	1799	1			T5	3		T6	7		T7	11
values[4]	1907	1			T11	6		T19	2		T6	7
values[5]	1876	1			T6	6		T7	10		T44	7
values[6]	1766	1			T5	1		T11	8		T6	2
values[7]	1752	1			T6	5		T7	17		T44	9
values[8]	12161	1			T9	14		T17	4		T5	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45273

1

T9

14

T15

20

T17

4

auto[1]

29029

1

T5

27

T46

7

T44

716

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

71695

1

T9

14

T15

20

T17

4

write

2607

1

T5

4

T6

9

T7

14

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

24084

1

T9

6

T15

20

T5

8

valids[0x1]

50218

1

T9

8

T17

4

T5

19

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1928	1			T5	3		T11	2		T6	7
internal_process_ops[0x5a]	1811	1			T5	2		T6	3		T7	11
internal_process_ops[0x05]	27652	1			T5	7		T6	40		T7	333
internal_process_ops[0x35]	1899	1			T5	1		T6	3		T7	8
internal_process_ops[0x15]	1897	1			T11	4		T6	5		T7	11
internal_process_ops[0x03]	1446	1			T6	7		T7	14		T44	5
internal_process_ops[0x0b]	1447	1			T9	8		T6	8		T7	10
internal_process_ops[0x3b]	1438	1			T5	1		T6	2		T7	16
internal_process_ops[0x6b]	1403	1			T11	2		T19	2		T6	6
internal_process_ops[0xbb]	1544	1			T11	8		T19	6		T6	5
internal_process_ops[0xeb]	1458	1			T9	6		T19	2		T6	7

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72955

1

T9

14

T15

20

T17

4

auto[1]

1347

1

T5

4

T6

5

T7

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71808

1

T9

14

T15

20

T17

4

auto[1]

2494

1

T5

3

T6

12

T7

14

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

15113

1

T15

20

T17

2

T19

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

10499

1

T11

8

T6

26

T7

209

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2909

1

T19

6

T6

15

T7

26

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2704

1

T11

4

T6

16

T7

24

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

3685

1

T9

8

T17

2

T19

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

3061

1

T6

7

T7

30

T18

16

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

3081

1

T9

6

T19

2

T6

13

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2679

1

T11

14

T6

14

T7

28

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

91

1

T6

1

T20

1

T231

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

82

1

T6

1

T18

2

T20

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

70

1

T32

1

T232

2

T233

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

116

1

T7

1

T18

1

T20

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

108

1

T7

1

T18

1

T20

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

99

1

T7

2

T20

2

T31

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

94

1

T6

3

T27

1

T29

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

99

1

T6

3

T20

3

T26

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

142

1

T22

1

T20

4

T31

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

84

1

T20

3

T27

3

T30

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

81

1

T27

1

T29

2

T31

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

112

1

T6

1

T7

1

T20

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

98

1

T7

6

T18

1

T20

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

76

1

T7

3

T29

1

T31

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

79

1

T32

2

T234

2

T235

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

111

1

T22

1

T31

1

T32

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10653

1

T5

11

T44

376

T45

125

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7537

1

T5

1

T44

141

T45

195

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1589

1

T44

19

T200

6

T45

27

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1412

1

T5

1

T44

35

T45

24

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1991

1

T44

41

T199

4

T45

35

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1742

1

T5

8

T44

34

T45

46

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1596

1

T5

2

T46

7

T44

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1444

1

T44

27

T45

33

T28

34

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

58

1

T45

1

T28

1

T159

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

102

1

T5

1

T44

2

T45

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

75

1

T44

5

T45

2

T159

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

59

1

T44

2

T28

2

T150

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

80

1

T45

2

T159

3

T161

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

77

1

T44

1

T45

5

T28

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

57

1

T44

1

T28

1

T161

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

66

1

T45

2

T28

1

T161

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

50

1

T28

3

T236

2

T237

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

56

1

T44

2

T45

1

T238

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

60

1

T44

2

T45

1

T150

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

70

1

T5

1

T44

2

T28

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

68

1

T44

1

T45

1

T28

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

78

1

T45

6

T28

1

T159

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

49

1

T44

5

T28

1

T239

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

60

1

T5

2

T44

1

T45

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	5906	1			T15	20		T19	2		T6	28
auto[0]	values[0]	valids[0x1]	23541	1			T11	6		T19	2		T6	82
auto[0]	values[1]	valids[0x1]	787	1			T6	4		T7	7		T18	4
auto[0]	values[2]	valids[0x0]	736	1			T11	2		T6	1		T7	4
auto[0]	values[2]	valids[0x1]	391	1			T6	5		T7	4		T20	2
auto[0]	values[3]	valids[0x0]	774	1			T6	6		T7	7		T18	5
auto[0]	values[3]	valids[0x1]	430	1			T6	1		T7	4		T18	2
auto[0]	values[4]	valids[0x0]	800	1			T11	4		T19	2		T6	6
auto[0]	values[4]	valids[0x1]	425	1			T11	2		T6	1		T7	7
auto[0]	values[5]	valids[0x0]	837	1			T6	3		T7	9		T18	7
auto[0]	values[5]	valids[0x1]	419	1			T6	3		T7	1		T18	3
auto[0]	values[6]	valids[0x0]	747	1			T11	8		T6	2		T7	6
auto[0]	values[6]	valids[0x1]	402	1			T7	4		T22	1		T20	9
auto[0]	values[7]	valids[0x0]	677	1			T6	4		T7	13		T18	4
auto[0]	values[7]	valids[0x1]	446	1			T6	1		T7	4		T18	1
auto[0]	values[8]	valids[0x0]	4940	1			T9	6		T11	4		T19	10
auto[0]	values[8]	valids[0x1]	3015	1			T9	8		T17	4		T6	7
auto[1]	values[0]	valids[0x0]	3909	1			T5	1		T44	72		T45	81
auto[1]	values[0]	valids[0x1]	16583	1			T5	17		T44	498		T45	279
auto[1]	values[1]	valids[0x1]	552	1			T44	12		T45	17		T28	16
auto[1]	values[2]	valids[0x0]	423	1			T5	3		T44	14		T45	12
auto[1]	values[2]	valids[0x1]	213	1			T44	1		T200	2		T45	3
auto[1]	values[3]	valids[0x0]	382	1			T5	3		T44	7		T200	5
auto[1]	values[3]	valids[0x1]	213	1			T44	4		T45	9		T28	6
auto[1]	values[4]	valids[0x0]	413	1			T44	4		T200	7		T45	3
auto[1]	values[4]	valids[0x1]	269	1			T44	6		T45	8		T28	3
auto[1]	values[5]	valids[0x0]	348	1			T44	3		T45	1		T28	7
auto[1]	values[5]	valids[0x1]	272	1			T44	4		T45	4		T28	7
auto[1]	values[6]	valids[0x0]	371	1			T5	1		T44	3		T45	24
auto[1]	values[6]	valids[0x1]	246	1			T44	5		T45	1		T28	2
auto[1]	values[7]	valids[0x0]	360	1			T44	4		T45	2		T28	6
auto[1]	values[7]	valids[0x1]	269	1			T44	5		T45	2		T28	7
auto[1]	values[8]	valids[0x0]	2461	1			T46	7		T44	49		T199	6
auto[1]	values[8]	valids[0x1]	1745	1			T5	2		T44	25		T199	1