Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21815

1

T9

17

T15

11

T17

1

auto[1]

25733

1

T5

7

T6

37

T7

322

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16450

1

T9

17

T15

11

T17

1

auto[1]

31098

1

T5

8

T6

48

T7

352

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	7028	1			T9	6		T17	1		T5	4
auto[524288:1048575]	5517	1			T9	7		T5	4		T6	14
auto[1048576:1572863]	6699	1			T9	1		T15	1		T6	6
auto[1572864:2097151]	5658	1			T9	2		T15	4		T6	6
auto[2097152:2621439]	6098	1			T15	1		T6	1		T7	41
auto[2621440:3145727]	5477	1			T15	2		T6	1		T7	79
auto[3145728:3670015]	5939	1			T9	1		T15	1		T5	9
auto[3670016:4194303]	5132	1			T15	2		T5	1		T6	50

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46947

1

T9

17

T15

11

T17

1

auto[1]

601

1

T5

1

T44

12

T20

17

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23723

1

T9

16

T15

4

T17

1

auto[1]

23825

1

T9

1

T15

7

T5

3

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	1398	1			T9	6		T17	1		T5	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	762	1			T5	1		T6	3		T7	3
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	804	1			T9	7		T5	1		T6	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	436	1			T5	1		T6	3		T7	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	848	1			T9	1		T6	3		T7	11
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	475	1			T6	1		T7	7		T20	9
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	890	1			T9	2		T15	1		T6	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	492	1			T6	1		T7	3		T44	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	823	1			T15	1		T7	2		T137	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	450	1			T23	3		T44	5		T20	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	796	1			T15	2		T7	2		T18	8
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	462	1			T6	1		T7	4		T18	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	806	1			T5	2		T7	2		T46	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	444	1			T5	2		T7	1		T44	7
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	873	1			T6	17		T7	5		T46	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	477	1			T6	6		T7	3		T44	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	809	1			T6	1		T7	7		T44	9
auto[0]	auto[1]	auto[0:524287]	auto[1]	450	1			T7	3		T44	4		T18	2
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	832	1			T6	2		T7	1		T23	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	477	1			T6	2		T23	2		T20	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	868	1			T15	1		T6	1		T7	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	519	1			T6	1		T7	4		T44	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	840	1			T15	3		T6	1		T7	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	494	1			T7	1		T23	1		T44	7
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	896	1			T6	1		T7	2		T46	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	510	1			T7	2		T44	5		T18	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	855	1			T7	5		T23	2		T24	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	473	1			T7	4		T44	3		T18	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	790	1			T9	1		T15	1		T5	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	465	1			T6	2		T7	5		T23	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	828	1			T15	2		T5	1		T6	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	473	1			T6	3		T7	3		T44	6
auto[1]	auto[0]	auto[0:524287]	auto[0]	182	1			T5	1		T6	2		T7	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1688	1			T5	1		T6	7		T7	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	129	1			T5	1		T6	1		T44	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1074	1			T5	1		T6	2		T44	27
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	176	1			T7	3		T20	4		T45	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1852	1			T7	37		T20	50		T45	26
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	173	1			T6	1		T7	2		T44	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1543	1			T6	1		T7	75		T44	14
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	147	1			T44	2		T27	2		T232	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1382	1			T44	32		T27	22		T232	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	154	1			T7	1		T18	2		T20	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1334	1			T7	54		T18	69		T20	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	145	1			T5	1		T44	4		T20	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1341	1			T5	2		T44	110		T20	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	149	1			T6	3		T20	3		T28	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1018	1			T6	7		T20	41		T28	10
auto[1]	auto[1]	auto[0:524287]	auto[0]	151	1			T44	2		T28	2		T31	4
auto[1]	auto[1]	auto[0:524287]	auto[1]	1588	1			T44	11		T28	2		T31	67
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	151	1			T6	1		T20	2		T45	5
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1614	1			T6	1		T20	26		T45	19
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	174	1			T44	3		T20	1		T28	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1787	1			T44	26		T20	14		T28	5
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	152	1			T44	1		T20	1		T45	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1074	1			T44	1		T20	25		T45	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	171	1			T7	2		T44	4		T20	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1719	1			T7	33		T44	61		T20	35
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	158	1			T7	1		T22	1		T20	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1245	1			T7	8		T22	1		T20	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	146	1			T6	1		T7	3		T44	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1802	1			T6	1		T7	88		T44	24
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	136	1			T6	3		T7	1		T44	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1178	1			T6	6		T7	10		T44	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	11158	1			T9	16		T15	4		T17	1
auto[0]	auto[0]	auto[1]	78	1			T44	1		T20	2		T45	1
auto[0]	auto[1]	auto[0]	10481	1			T9	1		T15	7		T5	3
auto[0]	auto[1]	auto[1]	98	1			T44	4		T20	2		T31	1
auto[1]	auto[0]	auto[0]	12277	1			T5	6		T6	24		T7	176
auto[1]	auto[0]	auto[1]	210	1			T5	1		T44	3		T20	8
auto[1]	auto[1]	auto[0]	13031	1			T6	13		T7	146		T44	137
auto[1]	auto[1]	auto[1]	215	1			T44	4		T20	5		T45	2