Group : spi_device_env_pkg::spi_device_env_cov::fw_tx_fifo_size_cg
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Group : spi_device_env_pkg::spi_device_env_cov::fw_tx_fifo_size_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv



Summary for Group spi_device_env_pkg::spi_device_env_cov::fw_tx_fifo_size_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::fw_tx_fifo_size_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_tx_size 8 0 8 100.00 100 1 1 0


Summary for Variable cp_tx_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_tx_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
specific_sizes[4] 34381 1 T12 1830 T49 1675 T57 422
specific_sizes[2048] 1308 1 T291 41 T292 3 T293 28
specific_sizes[4092] 1532 1 T220 260 T294 674 T295 199
sizes[0] 504355 1 T12 1830 T13 1263 T14 14488
sizes[1] 450905 1 T53 379 T296 65 T223 2
sizes[2] 231355 1 T100 552 T247 5616 T297 1063
sizes[3] 24377 1 T298 628 T150 685 T299 1656
sizes[4] 2446 1 T220 260 T300 1 T294 674

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%