Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25568

1

T9

14

T15

20

T17

4

auto[1]

19705

1

T11

26

T6

70

T7

293

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5985	1			T7	154		T18	162		T21	30
values[1]	6114	1			T6	32		T24	10		T284	10
values[2]	5947	1			T15	20		T19	16		T7	204
values[3]	5426	1			T11	26		T6	47		T7	112
values[4]	5344	1			T6	40		T7	92		T23	18
values[5]	5263	1			T17	4		T6	35		T7	20
values[6]	5444	1			T7	40		T34	2		T22	27
values[7]	5750	1			T9	14		T6	23		T22	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5393	1			T7	132		T18	56		T25	4
values[1]	6273	1			T17	4		T6	20		T7	20
values[2]	5256	1			T15	20		T6	35		T7	133
values[3]	5718	1			T6	52		T7	48		T137	8
values[4]	6265	1			T19	16		T6	27		T7	174
values[5]	6020	1			T6	43		T7	40		T23	18
values[6]	5307	1			T9	14		T11	26		T18	20
values[7]	5041	1			T7	75		T18	20		T284	10

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	329	1			T18	13		T21	30		T20	13
auto[0]	values[0]	values[1]	507	1			T7	7		T301	24		T29	40
auto[0]	values[0]	values[2]	412	1			T20	41		T31	17		T302	14
auto[0]	values[0]	values[3]	392	1			T18	12		T29	9		T32	37
auto[0]	values[0]	values[4]	583	1			T7	108		T18	15		T32	67
auto[0]	values[0]	values[5]	346	1			T7	16		T18	9		T27	10
auto[0]	values[0]	values[6]	355	1			T18	12		T20	10		T248	25
auto[0]	values[0]	values[7]	494	1			T20	8		T32	12		T233	91
auto[0]	values[1]	values[0]	378	1			T27	9		T232	13		T234	33
auto[0]	values[1]	values[1]	601	1			T27	11		T303	10		T232	14
auto[0]	values[1]	values[2]	341	1			T20	13		T30	14		T31	14
auto[0]	values[1]	values[3]	526	1			T6	25		T231	15		T304	22
auto[0]	values[1]	values[4]	549	1			T20	15		T27	35		T286	4
auto[0]	values[1]	values[5]	295	1			T24	10		T273	8		T233	12
auto[0]	values[1]	values[6]	306	1			T20	9		T29	13		T289	30
auto[0]	values[1]	values[7]	390	1			T284	10		T32	14		T231	12
auto[0]	values[2]	values[0]	290	1			T18	30		T31	10		T232	6
auto[0]	values[2]	values[1]	318	1			T27	14		T305	16		T233	13
auto[0]	values[2]	values[2]	277	1			T15	20		T7	15		T260	8
auto[0]	values[2]	values[3]	267	1			T137	8		T31	12		T232	10
auto[0]	values[2]	values[4]	421	1			T19	16		T7	12		T27	19
auto[0]	values[2]	values[5]	460	1			T232	20		T306	28		T307	2
auto[0]	values[2]	values[6]	464	1			T31	71		T32	17		T128	9
auto[0]	values[2]	values[7]	462	1			T7	13		T32	10		T308	10
auto[0]	values[3]	values[0]	256	1			T7	47		T25	4		T28	16
auto[0]	values[3]	values[1]	553	1			T20	68		T29	10		T231	68
auto[0]	values[3]	values[2]	368	1			T267	4		T232	12		T233	10
auto[0]	values[3]	values[3]	339	1			T231	11		T309	2		T310	16
auto[0]	values[3]	values[4]	407	1			T6	9		T232	36		T128	7
auto[0]	values[3]	values[5]	627	1			T6	13		T7	17		T18	15
auto[0]	values[3]	values[6]	397	1			T20	8		T30	10		T31	67
auto[0]	values[3]	values[7]	186	1			T18	6		T248	10		T311	18
auto[0]	values[4]	values[0]	544	1			T31	17		T32	61		T231	24
auto[0]	values[4]	values[1]	570	1			T6	11		T20	12		T31	14
auto[0]	values[4]	values[2]	264	1			T7	8		T32	20		T251	12
auto[0]	values[4]	values[3]	333	1			T6	13		T7	40		T27	9
auto[0]	values[4]	values[4]	368	1			T7	12		T29	17		T31	11
auto[0]	values[4]	values[5]	410	1			T23	18		T70	2		T232	10
auto[0]	values[4]	values[6]	251	1			T288	15		T253	50		T312	2
auto[0]	values[4]	values[7]	299	1			T288	12		T313	21		T314	16
auto[0]	values[5]	values[0]	400	1			T7	12		T232	10		T233	9
auto[0]	values[5]	values[1]	405	1			T17	4		T20	50		T315	2
auto[0]	values[5]	values[2]	294	1			T6	26		T20	11		T71	14
auto[0]	values[5]	values[3]	422	1			T18	8		T20	9		T29	16
auto[0]	values[5]	values[4]	715	1			T32	16		T232	12		T316	10
auto[0]	values[5]	values[5]	338	1			T272	10		T20	19		T231	17
auto[0]	values[5]	values[6]	346	1			T30	11		T231	13		T88	13
auto[0]	values[5]	values[7]	270	1			T231	15		T317	2		T288	51
auto[0]	values[6]	values[0]	463	1			T7	11		T20	8		T32	10
auto[0]	values[6]	values[1]	419	1			T34	2		T20	25		T27	9
auto[0]	values[6]	values[2]	426	1			T251	14		T217	34		T89	13
auto[0]	values[6]	values[3]	362	1			T253	8		T318	13		T319	13
auto[0]	values[6]	values[4]	369	1			T7	11		T32	44		T320	6
auto[0]	values[6]	values[5]	362	1			T232	16		T248	43		T197	39
auto[0]	values[6]	values[6]	291	1			T27	14		T311	8		T321	11
auto[0]	values[6]	values[7]	344	1			T22	14		T31	43		T253	36
auto[0]	values[7]	values[0]	548	1			T20	12		T232	9		T233	15
auto[0]	values[7]	values[1]	366	1			T252	14		T319	8		T197	7
auto[0]	values[7]	values[2]	349	1			T22	12		T30	12		T31	6
auto[0]	values[7]	values[3]	421	1			T20	8		T233	14		T285	34
auto[0]	values[7]	values[4]	441	1			T303	16		T233	166		T235	10
auto[0]	values[7]	values[5]	392	1			T6	10		T20	9		T233	11
auto[0]	values[7]	values[6]	606	1			T9	14		T29	5		T31	8
auto[0]	values[7]	values[7]	284	1			T157	20		T29	17		T32	9
auto[1]	values[0]	values[0]	248	1			T18	7		T20	7		T319	16
auto[1]	values[0]	values[1]	255	1			T7	13		T29	7		T231	8
auto[1]	values[0]	values[2]	299	1			T20	5		T31	6		T155	11
auto[1]	values[0]	values[3]	331	1			T18	58		T29	15		T32	10
auto[1]	values[0]	values[4]	357	1			T7	6		T18	5		T32	7
auto[1]	values[0]	values[5]	301	1			T7	4		T18	23		T27	10
auto[1]	values[0]	values[6]	528	1			T18	8		T20	48		T248	77
auto[1]	values[0]	values[7]	248	1			T20	12		T32	8		T233	22
auto[1]	values[1]	values[0]	264	1			T27	11		T232	11		T234	7
auto[1]	values[1]	values[1]	303	1			T27	16		T303	10		T232	6
auto[1]	values[1]	values[2]	450	1			T20	7		T30	15		T31	6
auto[1]	values[1]	values[3]	302	1			T6	7		T231	5		T89	6
auto[1]	values[1]	values[4]	330	1			T20	43		T27	9		T155	8
auto[1]	values[1]	values[5]	395	1			T233	62		T231	8		T88	9
auto[1]	values[1]	values[6]	219	1			T20	13		T29	10		T248	24
auto[1]	values[1]	values[7]	465	1			T32	6		T257	34		T73	12
auto[1]	values[2]	values[0]	177	1			T18	6		T31	16		T232	16
auto[1]	values[2]	values[1]	446	1			T27	6		T233	110		T248	11
auto[1]	values[2]	values[2]	485	1			T7	94		T158	22		T232	8
auto[1]	values[2]	values[3]	339	1			T26	16		T31	69		T232	10
auto[1]	values[2]	values[4]	304	1			T7	8		T27	6		T232	13
auto[1]	values[2]	values[5]	556	1			T232	28		T88	9		T253	65
auto[1]	values[2]	values[6]	165	1			T31	7		T32	3		T128	11
auto[1]	values[2]	values[7]	516	1			T7	62		T32	143		T288	67
auto[1]	values[3]	values[0]	257	1			T7	45		T28	6		T32	8
auto[1]	values[3]	values[1]	268	1			T20	8		T29	10		T231	6
auto[1]	values[3]	values[2]	252	1			T232	10		T233	19		T231	4
auto[1]	values[3]	values[3]	358	1			T231	71		T248	6		T321	9
auto[1]	values[3]	values[4]	314	1			T6	18		T232	20		T128	17
auto[1]	values[3]	values[5]	282	1			T6	7		T7	3		T18	26
auto[1]	values[3]	values[6]	389	1			T11	26		T20	65		T30	10
auto[1]	values[3]	values[7]	173	1			T18	14		T248	66		T311	7
auto[1]	values[4]	values[0]	442	1			T31	9		T32	17		T231	29
auto[1]	values[4]	values[1]	340	1			T6	9		T20	8		T31	6
auto[1]	values[4]	values[2]	143	1			T7	16		T32	7		T251	15
auto[1]	values[4]	values[3]	340	1			T6	7		T7	8		T27	33
auto[1]	values[4]	values[4]	254	1			T7	8		T29	20		T31	9
auto[1]	values[4]	values[5]	446	1			T232	10		T288	125		T266	25
auto[1]	values[4]	values[6]	159	1			T288	5		T253	9		T313	31
auto[1]	values[4]	values[7]	181	1			T288	22		T313	15		T314	9
auto[1]	values[5]	values[0]	242	1			T7	8		T232	10		T233	56
auto[1]	values[5]	values[1]	234	1			T20	14		T155	7		T322	12
auto[1]	values[5]	values[2]	130	1			T6	9		T20	9		T89	9
auto[1]	values[5]	values[3]	306	1			T18	12		T20	39		T29	9
auto[1]	values[5]	values[4]	347	1			T32	4		T232	12		T235	11
auto[1]	values[5]	values[5]	264	1			T20	8		T231	3		T235	10
auto[1]	values[5]	values[6]	291	1			T30	9		T231	7		T323	20
auto[1]	values[5]	values[7]	259	1			T231	18		T324	10		T288	18
auto[1]	values[6]	values[0]	312	1			T7	9		T20	27		T32	22
auto[1]	values[6]	values[1]	413	1			T20	18		T27	11		T32	98
auto[1]	values[6]	values[2]	408	1			T251	6		T89	7		T320	8
auto[1]	values[6]	values[3]	428	1			T253	85		T318	7		T319	14
auto[1]	values[6]	values[4]	250	1			T7	9		T32	10		T320	25
auto[1]	values[6]	values[5]	166	1			T232	4		T248	11		T197	6
auto[1]	values[6]	values[6]	163	1			T27	6		T325	22		T311	12
auto[1]	values[6]	values[7]	268	1			T22	13		T31	13		T253	8
auto[1]	values[7]	values[0]	243	1			T20	12		T232	11		T233	5
auto[1]	values[7]	values[1]	275	1			T256	28		T252	6		T319	19
auto[1]	values[7]	values[2]	358	1			T22	10		T30	11		T31	44
auto[1]	values[7]	values[3]	252	1			T20	12		T233	6		T89	6
auto[1]	values[7]	values[4]	256	1			T303	4		T233	30		T235	25
auto[1]	values[7]	values[5]	380	1			T6	13		T20	11		T233	9
auto[1]	values[7]	values[6]	377	1			T29	20		T31	25		T232	7
auto[1]	values[7]	values[7]	202	1			T29	3		T32	11		T251	8