Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	12	0	12	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=11}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	8676431	1			T4	1		T1	2		T9	1
all_pins[1]	8676431	1			T4	1		T1	2		T9	1
all_pins[2]	8676431	1			T4	1		T1	2		T9	1
all_pins[3]	8676431	1			T4	1		T1	2		T9	1
all_pins[4]	8676431	1			T4	1		T1	2		T9	1
all_pins[5]	8676431	1			T4	1		T1	2		T9	1
all_pins[6]	8676431	1			T4	1		T1	2		T9	1
all_pins[7]	8676431	1			T4	1		T1	2		T9	1
all_pins[8]	8676431	1			T4	1		T1	2		T9	1
all_pins[9]	8676431	1			T4	1		T1	2		T9	1
all_pins[10]	8676431	1			T4	1		T1	2		T9	1
all_pins[11]	8676431	1			T4	1		T1	2		T9	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	103912089	1			T4	12		T1	23		T9	12
values[0x1]	205083	1			T1	1		T3	1		T12	1
transitions[0x0=>0x1]	203858	1			T1	1		T3	1		T12	1
transitions[0x1=>0x0]	203867	1			T1	1		T3	1		T12	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	8675897	1			T4	1		T1	2		T9	1
all_pins[0]	values[0x1]	534	1			T80	4		T86	3		T87	2
all_pins[0]	transitions[0x0=>0x1]	340	1			T80	3		T86	2		T87	2
all_pins[0]	transitions[0x1=>0x0]	187425	1			T3	1		T86	3		T87	1
all_pins[1]	values[0x0]	8488812	1			T4	1		T1	2		T9	1
all_pins[1]	values[0x1]	187619	1			T3	1		T80	1		T86	4
all_pins[1]	transitions[0x0=>0x1]	187498	1			T3	1		T80	1		T86	4
all_pins[1]	transitions[0x1=>0x0]	453	1			T1	1		T12	1		T79	2
all_pins[2]	values[0x0]	8675857	1			T4	1		T1	1		T9	1
all_pins[2]	values[0x1]	574	1			T1	1		T12	1		T79	2
all_pins[2]	transitions[0x0=>0x1]	544	1			T1	1		T12	1		T86	1
all_pins[2]	transitions[0x1=>0x0]	86	1			T79	1		T80	2		T86	1
all_pins[3]	values[0x0]	8676315	1			T4	1		T1	2		T9	1
all_pins[3]	values[0x1]	116	1			T79	3		T80	2		T86	2
all_pins[3]	transitions[0x0=>0x1]	93	1			T79	3		T80	2		T86	1
all_pins[3]	transitions[0x1=>0x0]	414	1			T80	1		T86	2		T229	2
all_pins[4]	values[0x0]	8675994	1			T4	1		T1	2		T9	1
all_pins[4]	values[0x1]	437	1			T80	1		T86	3		T87	1
all_pins[4]	transitions[0x0=>0x1]	231	1			T80	1		T86	1		T87	1
all_pins[4]	transitions[0x1=>0x0]	2054	1			T79	1		T80	2		T228	1
all_pins[5]	values[0x0]	8674171	1			T4	1		T1	2		T9	1
all_pins[5]	values[0x1]	2260	1			T79	1		T80	2		T86	2
all_pins[5]	transitions[0x0=>0x1]	2243	1			T80	1		T86	2		T228	1
all_pins[5]	transitions[0x1=>0x0]	2009	1			T80	1		T86	3		T87	2
all_pins[6]	values[0x0]	8674405	1			T4	1		T1	2		T9	1
all_pins[6]	values[0x1]	2026	1			T79	1		T80	2		T86	3
all_pins[6]	transitions[0x0=>0x1]	1631	1			T79	1		T80	1		T86	2
all_pins[6]	transitions[0x1=>0x0]	403	1			T80	2		T86	1		T87	3
all_pins[7]	values[0x0]	8675633	1			T4	1		T1	2		T9	1
all_pins[7]	values[0x1]	798	1			T80	3		T86	2		T87	4
all_pins[7]	transitions[0x0=>0x1]	659	1			T80	3		T86	2		T87	4
all_pins[7]	transitions[0x1=>0x0]	170	1			T80	2		T86	2		T87	2
all_pins[8]	values[0x0]	8676122	1			T4	1		T1	2		T9	1
all_pins[8]	values[0x1]	309	1			T80	2		T86	2		T87	2
all_pins[8]	transitions[0x0=>0x1]	288	1			T80	2		T86	2		T228	1
all_pins[8]	transitions[0x1=>0x0]	90	1			T79	1		T80	1		T87	1
all_pins[9]	values[0x0]	8676320	1			T4	1		T1	2		T9	1
all_pins[9]	values[0x1]	111	1			T79	1		T80	1		T87	3
all_pins[9]	transitions[0x0=>0x1]	80	1			T79	1		T80	1		T87	3
all_pins[9]	transitions[0x1=>0x0]	50	1			T80	1		T86	1		T87	1
all_pins[10]	values[0x0]	8676350	1			T4	1		T1	2		T9	1
all_pins[10]	values[0x1]	81	1			T80	1		T86	1		T87	1
all_pins[10]	transitions[0x0=>0x1]	62	1			T86	1		T87	1		T228	1
all_pins[10]	transitions[0x1=>0x0]	10199	1			T79	1		T80	1		T86	1
all_pins[11]	values[0x0]	8666213	1			T4	1		T1	2		T9	1
all_pins[11]	values[0x1]	10218	1			T79	1		T80	2		T86	1
all_pins[11]	transitions[0x0=>0x1]	10189	1			T79	1		T229	2		T184	2
all_pins[11]	transitions[0x1=>0x0]	514	1			T80	3		T86	2		T87	2