Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	533	1			T6	2		T7	3		T18	4
auto[ReadAddrCrossIntoMailbox]	509	1			T6	6		T7	6		T18	4
auto[ReadAddrCrossOutOfMailbox]	475	1			T9	4		T6	5		T7	1
auto[ReadAddrCrossAllMailbox]	295	1			T6	3		T7	3		T18	1
auto[ReadAddrOutsideMailbox]	4998	1			T9	10		T11	10		T19	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3488

1

T9

7

T11

5

T19

5

auto[1]

3322

1

T9

7

T11

5

T19

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	1149	1			T6	7		T7	14		T18	4
read_ops[0x0b]	1149	1			T9	8		T6	8		T7	10
read_ops[0x3b]	1107	1			T6	2		T7	16		T24	2
read_ops[0x6b]	1068	1			T11	2		T19	2		T6	6
read_ops[0xbb]	1188	1			T11	8		T19	6		T6	5
read_ops[0xeb]	1149	1			T9	6		T19	2		T6	7

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	50	1			T7	1		T32	1		T315	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T6	1		T29	1		T233	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	41	1			T27	1		T32	1		T232	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	45	1			T6	2		T27	1		T31	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T6	1		T20	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	53	1			T20	1		T27	2		T233	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T7	1		T231	1		T248	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T20	1		T235	1		T155	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	425	1			T6	2		T7	6		T18	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	413	1			T6	1		T7	6		T18	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T32	1		T251	1		T232	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T18	1		T29	1		T31	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	42	1			T6	1		T20	2		T30	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	44	1			T7	2		T18	1		T31	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	42	1			T251	1		T233	1		T89	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	45	1			T32	3		T232	1		T233	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	40	1			T6	1		T20	1		T326	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T326	1		T280	1		T248	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	418	1			T9	4		T6	1		T7	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	420	1			T9	4		T6	5		T7	7
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T20	1		T32	1		T232	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T18	1		T27	1		T32	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	47	1			T6	1		T7	1		T20	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	38	1			T7	1		T20	1		T29	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T18	1		T29	1		T327	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T7	1		T29	1		T32	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	29	1			T7	1		T20	3		T27	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T6	1		T327	1		T233	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	414	1			T7	6		T24	1		T267	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	405	1			T7	6		T24	1		T18	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	58	1			T18	1		T29	2		T31	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	50	1			T20	1		T31	1		T233	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	45	1			T18	1		T20	1		T235	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T6	1		T7	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	42	1			T6	1		T31	1		T231	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T20	1		T31	1		T233	3
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T6	1		T29	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T231	1		T328	1		T329	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	391	1			T11	1		T19	1		T6	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	385	1			T11	1		T19	1		T6	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T7	2		T18	1		T32	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T29	1		T31	1		T32	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T29	1		T233	1		T235	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	47	1			T18	1		T29	1		T233	4
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	42	1			T6	3		T20	1		T251	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	43	1			T18	1		T32	1		T233	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	34	1			T31	2		T233	1		T280	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T32	2		T233	1		T89	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	478	1			T11	4		T19	3		T6	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	405	1			T11	4		T19	3		T6	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T6	1		T233	2		T302	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	52	1			T31	2		T32	3		T232	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	37	1			T6	1		T18	1		T233	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	60	1			T7	1		T20	1		T29	4
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	42	1			T9	2		T20	1		T231	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T9	2		T20	1		T233	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	31	1			T7	1		T18	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T20	1		T27	1		T327	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	444	1			T9	1		T19	1		T6	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	400	1			T9	1		T19	1		T6	1