Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5569	1			T6	32		T7	40		T18	20
values[1]	6211	1			T6	85		T7	24		T137	8
values[2]	5665	1			T7	77		T23	18		T18	36
values[3]	5177	1			T19	16		T7	209		T18	40
values[4]	5865	1			T15	20		T11	26		T6	40
values[5]	5363	1			T9	14		T17	4		T7	55
values[6]	5168	1			T6	20		T7	169		T284	10
values[7]	6255	1			T7	48		T18	32		T260	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5384	1			T9	14		T15	20		T7	57
values[1]	5254	1			T6	90		T7	20		T18	90
values[2]	5481	1			T7	75		T284	10		T20	95
values[3]	5654	1			T11	26		T18	20		T25	4
values[4]	5800	1			T6	40		T7	24		T18	36
values[5]	5294	1			T6	20		T7	183		T18	32
values[6]	6131	1			T19	16		T7	109		T23	18
values[7]	6275	1			T17	4		T6	27		T7	154

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44494

1

T9

14

T15

20

T17

4

auto[1]

779

1

T6

5

T7

7

T18

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	741	1			T18	20		T251	19		T231	20
auto[0]	values[0]	values[1]	466	1			T6	32		T27	25		T31	75
auto[0]	values[0]	values[2]	553	1			T20	20		T27	20		T252	62
auto[0]	values[0]	values[3]	647	1			T25	4		T20	20		T27	26
auto[0]	values[0]	values[4]	649	1			T20	22		T31	81		T235	35
auto[0]	values[0]	values[5]	867	1			T20	63		T31	20		T232	62
auto[0]	values[0]	values[6]	902	1			T29	22		T31	77		T306	28
auto[0]	values[0]	values[7]	644	1			T7	38		T29	25		T32	69
auto[0]	values[1]	values[0]	792	1			T137	8		T18	20		T232	19
auto[0]	values[1]	values[1]	888	1			T6	55		T18	20		T20	56
auto[0]	values[1]	values[2]	798	1			T32	47		T251	19		T233	91
auto[0]	values[1]	values[3]	804	1			T30	20		T31	19		T251	48
auto[0]	values[1]	values[4]	606	1			T7	24		T20	24		T74	16
auto[0]	values[1]	values[5]	551	1			T330	4		T88	20		T218	30
auto[0]	values[1]	values[6]	631	1			T22	27		T32	54		T331	2
auto[0]	values[1]	values[7]	1058	1			T6	27		T29	20		T303	20
auto[0]	values[2]	values[0]	797	1			T7	37		T332	2		T89	20
auto[0]	values[2]	values[1]	787	1			T7	20		T31	20		T128	20
auto[0]	values[2]	values[2]	477	1			T27	41		T31	25		T320	20
auto[0]	values[2]	values[3]	654	1			T231	74		T333	2		T334	8
auto[0]	values[2]	values[4]	883	1			T18	34		T20	45		T31	20
auto[0]	values[2]	values[5]	378	1			T7	20		T21	30		T32	20
auto[0]	values[2]	values[6]	647	1			T23	18		T233	20		T235	20
auto[0]	values[2]	values[7]	947	1			T20	56		T27	20		T30	20
auto[0]	values[3]	values[0]	645	1			T18	20		T34	2		T324	10
auto[0]	values[3]	values[1]	461	1			T32	57		T264	20		T276	20
auto[0]	values[3]	values[2]	652	1			T89	16		T335	20		T328	20
auto[0]	values[3]	values[3]	541	1			T18	20		T28	21		T248	27
auto[0]	values[3]	values[4]	763	1			T289	30		T89	34		T248	76
auto[0]	values[3]	values[5]	692	1			T7	94		T29	25		T232	31
auto[0]	values[3]	values[6]	727	1			T19	16		T32	20		T232	24
auto[0]	values[3]	values[7]	607	1			T7	113		T31	25		T73	12
auto[0]	values[4]	values[0]	776	1			T15	20		T27	20		T32	27
auto[0]	values[4]	values[1]	481	1			T18	70		T32	19		T325	22
auto[0]	values[4]	values[2]	771	1			T32	64		T231	20		T266	47
auto[0]	values[4]	values[3]	886	1			T11	26		T267	4		T27	20
auto[0]	values[4]	values[4]	672	1			T6	20		T233	70		T336	24
auto[0]	values[4]	values[5]	596	1			T6	18		T232	20		T231	20
auto[0]	values[4]	values[6]	811	1			T20	76		T32	36		T302	14
auto[0]	values[4]	values[7]	778	1			T24	10		T301	24		T32	32
auto[0]	values[5]	values[0]	511	1			T9	14		T31	32		T248	25
auto[0]	values[5]	values[1]	789	1			T29	37		T231	71		T155	20
auto[0]	values[5]	values[2]	418	1			T7	55		T20	34		T288	81
auto[0]	values[5]	values[3]	779	1			T32	45		T231	33		T337	66
auto[0]	values[5]	values[4]	800	1			T30	20		T233	17		T248	20
auto[0]	values[5]	values[5]	648	1			T20	47		T29	20		T233	19
auto[0]	values[5]	values[6]	772	1			T20	73		T338	8		T234	40
auto[0]	values[5]	values[7]	551	1			T17	4		T18	41		T272	10
auto[0]	values[6]	values[0]	308	1			T7	20		T30	26		T305	16
auto[0]	values[6]	values[1]	619	1			T22	21		T20	23		T26	12
auto[0]	values[6]	values[2]	745	1			T7	20		T284	10		T20	37
auto[0]	values[6]	values[3]	694	1			T27	20		T88	20		T197	73
auto[0]	values[6]	values[4]	484	1			T6	20		T32	19		T233	20
auto[0]	values[6]	values[5]	631	1			T7	18		T20	20		T327	14
auto[0]	values[6]	values[6]	804	1			T7	109		T31	36		T32	74
auto[0]	values[6]	values[7]	780	1			T233	28		T88	20		T252	102
auto[0]	values[7]	values[0]	746	1			T32	20		T233	196		T315	2
auto[0]	values[7]	values[1]	665	1			T64	2		T30	22		T31	47
auto[0]	values[7]	values[2]	973	1			T339	2		T158	22		T32	169
auto[0]	values[7]	values[3]	545	1			T20	20		T232	24		T307	2
auto[0]	values[7]	values[4]	852	1			T20	19		T71	14		T233	20
auto[0]	values[7]	values[5]	826	1			T7	47		T18	31		T260	8
auto[0]	values[7]	values[6]	746	1			T20	27		T32	20		T233	204
auto[0]	values[7]	values[7]	782	1			T29	69		T326	10		T303	20
auto[1]	values[0]	values[0]	8	1			T251	1		T340	1		T341	1
auto[1]	values[0]	values[1]	11	1			T342	2		T263	2		T343	1
auto[1]	values[0]	values[2]	10	1			T252	3		T329	2		T344	3
auto[1]	values[0]	values[3]	8	1			T27	1		T233	1		T253	1
auto[1]	values[0]	values[4]	9	1			T321	2		T269	1		T345	1
auto[1]	values[0]	values[5]	22	1			T20	1		T233	2		T323	4
auto[1]	values[0]	values[6]	21	1			T29	1		T31	1		T231	2
auto[1]	values[0]	values[7]	11	1			T7	2		T32	2		T88	1
auto[1]	values[1]	values[0]	1	1			T232	1		-	-		-	-
auto[1]	values[1]	values[1]	16	1			T6	3		T20	2		T319	4
auto[1]	values[1]	values[2]	14	1			T251	1		T233	2		T248	4
auto[1]	values[1]	values[3]	12	1			T31	1		T251	2		T288	2
auto[1]	values[1]	values[4]	7	1			T233	2		T253	1		T319	1
auto[1]	values[1]	values[5]	9	1			T197	1		T346	3		T347	1
auto[1]	values[1]	values[6]	8	1			T197	2		T344	1		T221	1
auto[1]	values[1]	values[7]	16	1			T197	2		T348	1		T321	1
auto[1]	values[2]	values[0]	7	1			T288	1		T348	4		T349	1
auto[1]	values[2]	values[1]	13	1			T329	1		T350	2		T351	1
auto[1]	values[2]	values[2]	12	1			T27	3		T31	1		T128	4
auto[1]	values[2]	values[3]	18	1			T263	2		T250	1		T352	1
auto[1]	values[2]	values[4]	16	1			T18	2		T20	1		T232	1
auto[1]	values[2]	values[5]	9	1			T257	6		T353	2		T354	1
auto[1]	values[2]	values[6]	5	1			T268	1		T355	2		T352	1
auto[1]	values[2]	values[7]	15	1			T20	2		T231	2		T197	1
auto[1]	values[3]	values[0]	12	1			T252	1		T356	1		T357	1
auto[1]	values[3]	values[1]	11	1			T32	1		T264	2		T358	3
auto[1]	values[3]	values[2]	14	1			T89	4		T314	2		T359	1
auto[1]	values[3]	values[3]	5	1			T28	1		T252	1		T329	1
auto[1]	values[3]	values[4]	15	1			T89	2		T269	1		T314	1
auto[1]	values[3]	values[5]	8	1			T7	1		T249	1		T360	1
auto[1]	values[3]	values[6]	13	1			T288	1		T356	2		T352	2
auto[1]	values[3]	values[7]	11	1			T7	1		T31	1		T232	5
auto[1]	values[4]	values[0]	5	1			T361	1		T362	3		T363	1
auto[1]	values[4]	values[1]	9	1			T32	1		T311	1		T353	1
auto[1]	values[4]	values[2]	12	1			T32	1		T319	1		T197	1
auto[1]	values[4]	values[3]	13	1			T233	1		T89	1		T319	1
auto[1]	values[4]	values[4]	18	1			T233	4		T89	2		T319	4
auto[1]	values[4]	values[5]	12	1			T6	2		T248	2		T319	1
auto[1]	values[4]	values[6]	14	1			T32	1		T319	1		T270	4
auto[1]	values[4]	values[7]	11	1			T253	1		T328	1		T311	1
auto[1]	values[5]	values[0]	12	1			T31	1		T248	1		T128	2
auto[1]	values[5]	values[1]	8	1			T348	1		T119	1		T364	1
auto[1]	values[5]	values[2]	3	1			T20	1		T119	1		T365	1
auto[1]	values[5]	values[3]	20	1			T32	2		T249	1		T348	2
auto[1]	values[5]	values[4]	15	1			T233	3		T348	5		T353	1
auto[1]	values[5]	values[5]	6	1			T20	1		T233	1		T235	3
auto[1]	values[5]	values[6]	12	1			T155	1		T288	1		T319	1
auto[1]	values[5]	values[7]	19	1			T232	5		T256	4		T252	2
auto[1]	values[6]	values[0]	7	1			T30	3		T311	1		T344	1
auto[1]	values[6]	values[1]	19	1			T22	1		T26	4		T88	1
auto[1]	values[6]	values[2]	9	1			T20	3		T366	2		T356	1
auto[1]	values[6]	values[3]	12	1			T197	1		T250	1		T367	2
auto[1]	values[6]	values[4]	6	1			T32	1		T288	1		T368	1
auto[1]	values[6]	values[5]	18	1			T7	2		T231	3		T268	2
auto[1]	values[6]	values[6]	7	1			T288	1		T250	2		T350	1
auto[1]	values[6]	values[7]	25	1			T233	1		T252	4		T348	5
auto[1]	values[7]	values[0]	16	1			T233	2		T248	1		T266	1
auto[1]	values[7]	values[1]	11	1			T30	1		T31	3		T197	1
auto[1]	values[7]	values[2]	20	1			T32	4		T234	5		T248	1
auto[1]	values[7]	values[3]	16	1			T319	1		T352	3		T357	3
auto[1]	values[7]	values[4]	5	1			T20	1		T128	1		T311	3
auto[1]	values[7]	values[5]	21	1			T7	1		T18	1		T233	1
auto[1]	values[7]	values[6]	11	1			T233	1		T311	1		T355	2
auto[1]	values[7]	values[7]	20	1			T29	2		T320	1		T311	2